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GTU Engineering Graphics & Design (3110013) Semester Semester 1 & 2 Summer 2025 Solved Paper

Complete step-by-step solutions for the GTU Summer 2025 Engineering Graphics & Design (3110013) exam paper, including orthographic, isometric, line projections, scales, and curves.

Introduction

This document provides complete, student-friendly, step-by-step solutions for the Gujarat Technological University (GTU) Summer 2025 examination in Engineering Graphics & Design (Subject Code: 3110013). Every question is thoroughly solved with standard technical drawing procedures, clear mathematical steps, detailed explanations, and labeled ASCII schematics where appropriate.

Paper Information

University
Gujarat Technological University
Department
First Year Engineering (Common)
Semester
Semester 1 & 2
Subject
Engineering Graphics & Design
Subject Code
3110013
Exam
Summer 2025
Year
2025

Questions and Solutions

Q.1 (a)

Question

Explain the difference between Ist angle and IIIrd angle projection method.

Solution

Definition

Both First Angle and Third Angle projection methods are standard orthographic projection systems used to represent three-dimensional objects on two-dimensional drawing planes using mutually perpendicular reference planes: the Horizontal Plane (HP) and the Vertical Plane (VP).

Key Differences

| Parameter | First Angle Projection Method | Third Angle Projection Method | | :--- | :--- | :--- | | Quadrant Position | The object is placed in the First Quadrant (above HP, in front of VP). | The object is placed in the Third Quadrant (below HP, behind VP). | | Relative Position | The object lies between the observer and the plane of projection. | The projection plane lies between the observer and the object. | | Nature of Planes | Projection planes are assumed to be non-transparent (opaque). | Projection planes are assumed to be transparent. | | Position of Views | Top View is drawn below the Front View (Elevation). Left Side View is drawn on the right-hand side of the Front View. | Top View is drawn above the Front View. Left Side View is drawn on the left-hand side of the Front View. | | Standard Usage | Widely used in India (Bureau of Indian Standards - BIS) and European countries (ISO). | Extensively used in USA, Canada, and Japan (ANSI/ASME standard). |

Standard Symbolic Representation

  • In First Angle projection, the symbol displays the smaller diameter base of a frustum of a cone facing away from the circular view when projected from the left.
  • In Third Angle projection, the frustum's smaller diameter base faces towards the circular view.

Q.1 (b)

Question

The distance between two cities is 250 km and is represented by a line of length 50mm on a map. Construct a scale to read 600 km and indicate a distance of 530 km on it.

Solution

1. Given Data

  • Actual distance between two cities = 250 km
  • Length of line on drawing = 50 mm
  • Maximum distance to be measured (M) = 600 km
  • Distance to be indicated = 530 km

2. Representative Fraction (R.F.)

R.F. = (Length on drawing / Actual distance) Actual distance = 250 km = 250 × 10^3 m = 250 × 10^5 cm = 250 × 10^6 mm R.F. = (50 mm / 250 × 10^6 mm) = (1 / 5,000,000) = 1 : 5,000,000

3. Length of Scale (L.O.S.)

Length of Scale = R.F. × Maximum distance to be measured L.O.S. = (1 / 5,000,000) × (600 × 10^6 mm) = (600 / 5) = 120 mm = 12 cm

4. Step-by-Step Construction Procedure

  1. Draw a horizontal straight line of length 120 mm and width 5 mm to form a scale bar.
  2. Divide this 120 mm long line into 6 equal parts. Each main division represents 600 / 6 = 100 km.
  3. Mark the primary zero at the end of the first main division. Number the primary divisions to the right of zero as 100, 200, 300, 400, 500 km.
  4. Divide the first sub-division (0 to 100 km on the left of zero) into 10 equal parts. Each small division represents 10 km. Number these subdivisions towards the left: 0, 10, 20, dots, 100 km.
  5. To indicate 530 km:
  • Take 500 km on the right side of 0 (5 main divisions).
  • Take 30 km on the left side of 0 (3 sub-divisions).
  • Mark the total distance of 500 + 30 = 530 km above the scale with extension lines and a dimension line with closed filled arrowheads.
  1. Print the Representative Fraction: R.F. = 1 : 5,000,000 beneath the scale.
  <------------------ 530 km ------------------>
  |                                            |
  100  50   0    100   200   300   400   500 km
  +----+----+----+-----+-----+-----+-----+-----+
  |////|////|    |     |     |     |     |     |
  +----+----+----+-----+-----+-----+-----+-----+
   (1 div = 10 km)       (1 div = 100 km)
        R.F. = 1 : 5,000,000,  L.O.S. = 120 mm

Q.1 (c)

Question

The foci of an ellipse are 120mm apart. The minor axis 72 mm long. Determine the length of the major axis and draw ellipse by oblong method.

Solution

1. Calculation of the Major Axis

  • Distance between foci (2c or F_1F_2) = 120 mm implies c = 60 mm
  • Length of minor axis (2b or CD) = 72 mm implies b = 36 mm
  • Let the length of major axis be 2a (AB), so the semi-major axis is a.

From the standard geometric property of an ellipse: a^2 = b^2 + c^2 a^2 = (36)^2 + (60)^2 = 1296 + 3600 = 4896 a = √(4896) ≈ 69.97 mm ≈ 70 mm Length of major axis 2a = 2 × 70 = 140 mm

2. Step-by-Step Construction by Oblong (Rectangle) Method

  1. Draw the axes: Draw a horizontal line AB = 140 mm (Major Axis) and bisect it perpendicularly at center O. Along this perpendicular, draw CD = 72 mm such that OC = OD = 36 mm (Minor Axis).
  2. Construct the bounding rectangle: Through points A and B, draw vertical lines. Through points C and D, draw horizontal lines. These lines intersect to form a rectangle of size 140 mm × 72 mm. Label the corners P, Q, R, S.
  3. Divide semi-axes into equal parts:
  • Divide the semi-major axis OA into 4 equal parts, labeled 1, 2, 3 from A towards O.
  • Divide the vertical side of the rectangle above A (i.e., line AP) into the same number of equal parts (4 parts), labeled 1', 2', 3' from A upwards to P.
  1. Locate points of the curve:
  • Join point C to points 1', 2', 3'.
  • Draw rays from point D passing through points 1, 2, 3 on the major axis, extending each to intersect the corresponding rays C1', C2', C3' at points P_1, P_2, P_3.
  • These intersection points lie on the ellipse in the top-left quadrant.
  1. Repeat for all four quadrants:
  • Repeat the identical division and intersection procedure for the other three quadrants (or reflect the points symmetrically across the major and minor axes).
  1. Draw the ellipse: Draw a smooth, continuous curve passing through A, P_1, P_2, P_3, C, dots, B, dots, D to complete the ellipse.

Q.2 (a)

Question

Differentiate in between Unidirectional system and Aligned system of dimensioning.

Solution

Overview

Dimensioning systems determine how numerical dimension values and notes are placed relative to the dimension lines on engineering drawings.

Key Differences

| Feature | Aligned System | Unidirectional System | | :--- | :--- | :--- | | Orientation of Text | Dimensions are placed parallel to the dimension lines. | Dimensions are always placed horizontally, regardless of the line direction. | | Reading Direction | The drawing is read from the bottom edge and from the right-hand edge. | The drawing is read exclusively from the bottom edge. | | Placement Relative to Line | Dimensions are written above and clear of unbroken dimension lines. | Dimension lines are broken near the center to insert the horizontal value. | | Convenience | Preferred in traditional manual engineering and architectural drawings. | Preferred on large engineering drawings and modern CAD drafting systems because it avoids tilting the sheet. |

Schematic Representation

        Aligned System                Unidirectional System
       -----------------             -----------------------
              50                                |   50   |
       |<------------->|                     |<----+---->|

       ^
       |                                       ^
    30 |                                    30 |  (always horizontal)
       |                                       |
       v                                       v

Q.2 (b)

Question

Draw the projection of following points on the same X-Y line. (1) Point A is 25 mm above HP and 30 mm behind V.P. (2) Point B is 20 mm above HP and on V.P. (3) Point C is 10 mm bellow HP and 25 mm behind V.P. (4) Point D is on HP and 40 mm in front of V.P.

Solution

Identification of Quadrants & Projections

In standard orthographic projections:

  • Front views are labeled with small lowercase letters with a prime (a', b', c', d').
  • Top views are labeled with lowercase letters without a prime (a, b, c, d).
  1. Point A (2nd Quadrant):
  • 25 mm above HP implies a' is 25 mm above the XY line.
  • 30 mm behind VP implies a is 30 mm above the XY line (both views lie above XY).
  1. Point B (In VP, above HP):
  • 20 mm above HP implies b' is 20 mm above the XY line.
  • On VP implies b is on the XY line.
  1. Point C (3rd Quadrant):
  • 10 mm below HP implies c' is 10 mm below the XY line.
  • 25 mm behind VP implies c is 25 mm above the XY line.
  1. Point D (In HP, in front of VP):
  • On HP implies d' is on the XY line.
  • 40 mm in front of VP implies d is 40 mm below the XY line.

Drawing Procedure

  1. Draw a continuous horizontal reference line and label it X-Y.
  2. Choose 4 distinct vertical projector lines spaced evenly (say 30 mm to 40 mm apart).
  3. On projector 1: Mark a' at 25 mm above XY, and a at 30 mm above XY.
  4. On projector 2: Mark b' at 20 mm above XY, and b on the XY line.
  5. On projector 3: Mark c at 25 mm above XY, and c' at 10 mm below XY.
  6. On projector 4: Mark d' on the XY line, and d at 40 mm below XY.
                       a (30)
                       |
                       |      c (25)
         a' (25)       |      |
         |             |      |
         |      b' (20)|      |
  -------+------+------+------+------+-------  X-Y line
                b             |      d'
                              |      |
                              c'(10) |
                                     |
                                     d (40)
  (Projector 1) (Projector 2) (Projector 3) (Projector 4)

Q.2 (c)

Question

A Line AB, 90 mm long, is inclined to H.P. by 30° and inclined to V.P. by 45º. The line is in first quadrant with Point A 15 mm above H.P. and 25 mm in front of V.P. Draw the projection of line AB.

Solution

1. Given Data

  • True Length (TL) = 90 mm
  • True inclination to HP (θ) = 30°
  • True inclination to VP (phi) = 45°
  • Point A: 15 mm above HP (a') and 25 mm in front of VP (a)
  • The line lies in the first quadrant.

2. Analytical Check for Locus Levels

  • Vertical height difference between ends: Δ h = TL sinθ = 90 sin 30° = 45 mm
  • Level of locus of b' = 15 + 45 = 60 mm above XY.
  • Plan length when inclined to HP: b_1 = TL cosθ = 90 cos 30° ≈ 77.94 mm
  • Horizontal depth difference between ends: Δ d = TL sinphi = 90 sin 45° ≈ 63.64 mm
  • Level of locus of b = 25 + 63.64 = 88.64 mm below XY.
  • Elevation length when inclined to VP: a'b_2' = TL cosphi = 90 cos 45° ≈ 63.64 mm

3. Step-by-Step Drawing Procedure

  1. Draw the reference line X-Y.
  2. Mark point a' at 15 mm above XY and point a at 25 mm below XY on the same vertical projector.
  3. Through a', draw a line at θ = 30° to the horizontal of true length 90 mm to get point b_1'. Through b_1', draw a horizontal dashed line: the locus of b' (at 60 mm above XY).
  4. Project b_1' vertically downward onto the horizontal line through a to locate b_1. Length ab_1 = 77.94 mm is the plan length (PL).
  5. Through a, draw a line at phi = 45° to the horizontal of true length 90 mm to get point b_2. Through b_2, draw a horizontal dashed line: the locus of b (at 88.6 mm below XY).
  6. Project b_2 vertically upward onto the horizontal line through a' to locate b_2'. Length a'b_2' = 63.64 mm is the elevation length (EL).
  7. With center a' and radius a'b_2', swing an arc to intersect the locus of b' at b'. Join a'b' (this is the final Front View).
  8. With center a and radius ab_1, swing an arc to intersect the locus of b at b. Join ab (this is the final Top View).
  9. Check: The points b' and b must lie strictly on the same vertical projector perpendicular to XY.

Q.2 (c) OR

Question

Draw a parabola by rectangle method, given its base as 90 mm and the height of axis is 75 mm.

Solution

1. Given Data

  • Base length (b) = 90 mm
  • Axis height (h) = 75 mm

2. Principle of Rectangle Method

In the rectangle method, a parabola is inscribed in a rectangle whose width equals the base and height equals the axis height. The vertex of the parabola is at the midpoint of the top horizontal edge.

3. Step-by-Step Construction Procedure

  1. Construct the Enclosing Rectangle:
  • Draw a horizontal base line AB = 90 mm.
  • Find the midpoint M of AB (AM = MB = 45 mm) and erect a perpendicular MV = 75 mm. Here V is the vertex of the parabola.
  • Complete the rectangle ABCD where AD = BC = 75 mm (vertical) and DC = 90 mm (horizontal passing through V).
  1. Divide the Sides into Equal Parts:
  • Divide the left-half base AM (or top half DV) into an equal number of parts, say 5 equal parts: 1, 2, 3, 4 starting from A to M.
  • Divide the left vertical edge AD into the same number of equal parts (5 equal parts): 1', 2', 3', 4' starting from A upward to D.
  1. Locate the Curve Points:
  • From points 1, 2, 3, 4 on the base, draw vertical lines parallel to the axis MV.
  • Join the vertex V to each of the points 1', 2', 3', 4' on the vertical edge AD.
  • The intersection of line V-1' with the vertical line through 1 gives point P_1.
  • The intersection of line V-2' with the vertical line through 2 gives point P_2.
  • Similarly, find points P_3 and P_4.
  1. Repeat for the Right Half:
  • Follow the identical procedure for the right half (rectangle MBCV) or transfer the points symmetrically across the central axis MV to get P_1', P_2', P_3', P_4'.
  1. Draw the Curve:
  • Join A, P_1, P_2, P_3, P_4, V, P_4', P_3', P_2', P_1', B using a smooth French curve to form the required parabola.

Q.3 (a)

Question

Define: (1) Involute (2) Spiral (3) Cycloid

Solution

1. Involute

An involute is the locus of a point on a perfectly taut, inextensible string as it unwinds from (or winds onto) the perimeter of a given plane curve or polygon (such as a circle, triangle, or square). In circles, it is widely used as the profile for standard gear teeth.

2. Spiral

A spiral (specifically Archemedian Spiral) is a plane curve traced by a point moving along a straight line at a uniform speed while the line rotates about a fixed point (called the pole) at a uniform angular velocity.

3. Cycloid

A cycloid is a plane curve generated by the locus of a fixed point on the circumference of a circle (called the generating circle) as it rolls without slipping along a fixed straight line (called the directing line).

Q.3 (b)

Question

A line AB 75mm long is incline at an angle of 45° to H.P. and 30° to V.P. One of its end point A is H.P. as well as in V.P. Determine its apparent angle with V.P.

Solution

1. Given Data

  • True Length (TL) = 75 mm
  • Inclination with HP (θ) = 45°
  • Inclination with VP (phi) = 30°
  • Position of point A: In HP and in VP implies a' and a both lie on the X-Y line at the same point.
  • Apparent angle with VP = β (angle made by the Top View ab with the XY line).

2. Mathematical Calculation

In orthographic projection of straight lines: cosβ = (TL cosphi / TL_h) = (Plan Length / True Plan Length) Alternatively, using the standard formula for apparent angle β: sinβ = (sinphi / cosθ) Substitute the given values: sinβ = (sin 30° / cos 45°) = frac{0.5}{frac{1}{√(2)}} = 0.5 × √(2) = frac{√(2)}{2} = frac{1}{√(2)} ≈ 0.7071 β = arcsin(0.7071) = 45°

3. Step-by-Step Graphical Construction

  1. Draw reference line X-Y and mark a common origin point a' equiv a on it.
  2. From a', draw a line at θ = 45° above XY of length 75 mm to locate b_1'.
  3. Project b_1' vertically downward onto the XY line to get b_1. The length ab_1 = 75 cos 45° = 75 × 0.7071 = 53.03 mm represents the Plan Length (PL).
  4. From a, draw a line at phi = 30° below XY of length 75 mm to locate b_2.
  5. Through b_2, draw a horizontal line parallel to XY: this is the locus of b at a distance of 75 sin 30° = 37.5 mm below XY.
  6. With center a and radius equal to ab_1 (53.03 mm), draw an arc to intersect the locus of b at point b.
  7. Join ab. This is the Top View of the line.
  8. Measure the angle between the Top View ab and the XY line: β = 45°.

Q.3 (c)

Question

In a slider crank mechanism, crank is 40mm and connecting rod is 160mm in length. The slider moves along a straight line passing through center of crank rotation. Trace the locus of midpoint P of connecting rod.

Solution

1. Given Data

  • Crank length (OA) = 40 mm
  • Connecting rod length (AB) = 160 mm
  • Midpoint P is located on AB such that AP = PB = 80 mm
  • Line of stroke of slider B passes through crank center O (in-line slider-crank mechanism).

2. Theory / Nature of Locus

For an in-line slider crank mechanism, the locus of any point on the connecting rod (other than the ends) is an ellipse.

3. Step-by-Step Construction Procedure

  1. Draw a horizontal centerline representing the line of stroke of slider B. Mark the crank center O on this line.
  2. With O as center and radius OA = 40 mm, draw the crank circle.
  3. Divide the crank circle into 12 equal angular parts (each 30°), labeled A_0, A_1, A_2, dots, A_{11}.
  4. For each crank position A_i:
  • Set a compass to the connecting rod length AB = 160 mm.
  • With center A_i, swing an arc to intersect the horizontal line of stroke to locate the slider position B_i.
  • Draw a thin straight line connecting A_i and B_i.
  • Find and mark the exact midpoint P_i along A_iB_i such that A_iP_i = 80 mm.
  1. Repeat this step for all 12 positions:
  • Position 0 (0°): A_0 is at (40, 0), B_0 is at (200, 0), P_0 is at (120, 0).
  • Position 6 (180°): A_6 is at (-40, 0), B_6 is at (120, 0), P_6 is at (40, 0).
  1. Connect all plotted points P_0, P_1, P_2, dots, P_{11} with a smooth, closed curve.
  2. Result: The resulting locus of point P is an ellipse having a major axis lying along the horizontal line of stroke of length (120 - 40) = 80 mm (equal to 2 × OA = 80 mm).

Q.3 (a) OR

Question

A line PQ 65 mm long is parallel to HP and 40mm below HP Its two ends P and Q are 25mm and 45mm behind VP respectively. Draw the Projections and find inclination of line with VP.

Solution

1. Given Data

  • True Length (TL) of line PQ = 65 mm
  • Line is parallel to HP implies θ = 0°; whole line is 40 mm below HP.
  • End P is 25 mm behind VP.
  • End Q is 45 mm behind VP.
  • Since both ends are below HP and behind VP, the line lies in the Third Quadrant.

2. Mathematical Calculation

In third quadrant:

  • Front view lies below the XY line.
  • Top view lies above the XY line.
  • Since the line is parallel to HP, its Front View is parallel to XY and its Top View shows the True Length (65 mm).

Let phi be the inclination with VP: sinphi = (Difference in distances from VP / TL) = (45 - 25 / 65) = (20 / 65) = (4 / 13) ≈ 0.3077 phi = arcsin(0.3077) ≈ 17.92° ≈ 18°

3. Step-by-Step Drawing Procedure

  1. Draw the reference line X-Y.
  2. Draw the Front View:
  • Since line PQ is 40 mm below HP, draw a line parallel to and 40 mm below XY.
  • The front view p'q' will lie entirely on this line.
  1. Draw the Top View:
  • Mark point p on a projector at 25 mm above the XY line.
  • Draw a horizontal locus line at 45 mm above XY representing the distance of end Q behind VP.
  • With center p and radius equal to true length 65 mm, swing an arc to intersect the locus line of Q at point q.
  • Join pq. This is the Top View.
  1. Complete the Front View:
  • From p, project vertically downward to intersect the line 40 mm below XY at p'.
  • From q, project vertically downward to intersect the line 40 mm below XY at q'.
  • Join p'q'. The line p'q' is horizontal and measures TL cosphi = 65 cos(17.92°) ≈ 61.85 mm.
  1. Measure phi: The angle made by Top View pq with the horizontal is phi ≈ 18°.

Q.3 (b) OR

Question

Construct the involute of circle of 30mm diameter for one turn.

Solution

1. Given Data

  • Diameter of circle (d) = 30 mm implies Radius (r) = 15 mm
  • Perimeter of circle (P) = Ï€ d = Ï€ × 30 ≈ 94.25 mm
  • Number of turns = 1 complete revolution

2. Step-by-Step Construction Procedure

  1. With center O and radius 15 mm, draw the generating circle.
  2. Divide the circle into 12 equal parts. Label the points around the circumference as 1, 2, 3, dots, 12 in clockwise order, where point 12 (or P_0) is at the lowest point of the circle.
  3. From point 12, draw a horizontal tangent line directed to the left (or right) of length equal to π d = 94.25 mm. Label the end point P_{12}.
  4. Divide this tangent line P_0P_{12} into 12 equal divisions labeled 1', 2', 3', dots, 12'. Each division has length 94.25 / 12 = 7.85 mm.
  5. At each point 1, 2, 3, dots, 11 on the circle, draw lines tangent to the circle in the unwinding direction (perpendicular to radii O1, O2, dots).
  6. Along the tangent drawn at point 1, mark distance 1-P_1 = P_0-1' = 7.85 mm.
  7. Along the tangent drawn at point 2, mark distance 2-P_2 = P_0-2' = 2 × 7.85 = 15.71 mm.
  8. Continue this process so that on tangent at point n, length n-P_n = n × 7.85 mm.
  9. Connect points P_0, P_1, P_2, dots, P_{12} with a smooth, continuous curve using a French curve.
  10. Label the resulting curve as the Involute of the Circle.

Q.3 (c) OR

Question

A line EF, 75 mm long, has its end E 20 mm below HP and 25 mm behind VP. The end F is 50 mm below H.P. and 65 mm behind VP Draw the projection of line EF and Find its inclination with HP and VP.

Solution

1. Given Data

  • True Length (TL) = 75 mm
  • Point E: 20 mm below HP (e' is 20 mm below XY), 25 mm behind VP (e is 25 mm above XY).
  • Point F: 50 mm below HP (f' is 50 mm below XY), 65 mm behind VP (f is 65 mm above XY).
  • Both ends are below HP and behind VP implies the line lies entirely in the Third Quadrant.

2. Mathematical Calculations

  • Difference in levels below HP: Δ h = 50 - 20 = 30 mm
  • True inclination with HP (θ):
    sinθ = (Δ h / TL) = (30 / 75) = 0.4 implies θ = arcsin(0.4) ≈ 23.58° ≈ 24°
  • Difference in distances behind VP: Δ d = 65 - 25 = 40 mm
  • True inclination with VP (phi):
    sinphi = (Δ d / TL) = (40 / 75) = (8 / 15) ≈ 0.5333 implies phi = arcsin(0.5333) ≈ 32.23° ≈ 32°

3. Step-by-Step Graphical Construction

  1. Draw the reference line X-Y.
  2. Choose a projector and mark:
  • e' at 20 mm below XY.
  • e at 25 mm above XY.
  1. Draw horizontal locus lines:
  • Locus of f': at 50 mm below XY (parallel to XY).
  • Locus of f: at 65 mm above XY (parallel to XY).
  1. Find θ and Plan Length (PL):
  • With center e' and radius equal to TL = 75 mm, swing an arc to cut the locus of f' at point f_1'.
  • Join e'f_1'. The angle made by e'f_1' with the horizontal is θ ≈ 23.6°.
  • Project f_1' vertically upward to the horizontal level of e (25 mm above XY) to find point f_1. The length ef_1 is the Plan Length (PL = 75 cos 23.58° ≈ 68.74 mm).
  1. Find phi and Elevation Length (EL):
  • With center e and radius equal to TL = 75 mm, swing an arc to cut the locus of f at point f_2.
  • Join ef_2. The angle made by ef_2 with the horizontal is phi ≈ 32.2°.
  • Project f_2 vertically downward to the horizontal level of e' (20 mm below XY) to find point f_2'. The length e'f_2' is the Elevation Length (EL = 75 cos 32.23° ≈ 63.44 mm).
  1. Final Projections:
  • With center e' and radius e'f_2', swing an arc to intersect the locus of f' at f'. Join e'f' (Front View).
  • With center e and radius ef_1, swing an arc to intersect the locus of f at f. Join ef (Top View).
  • Verify that f' and f lie on the exact same vertical projector line.

Q.4 (a)

Question

Draw the lateral development of a cone of base diameter 40mm and height 60mm.

Solution

1. Given Data

  • Base diameter (d) = 40 mm implies Base radius (r) = 20 mm
  • Axis height (h) = 60 mm

2. Calculations

  • Slant Height (R or L):
    R = √(r^2 + h^2) = √(20^2 + 60^2) = √(400 + 3600) = √(4000) ≈ 63.25 mm
  • Subtended Sector Angle (θ):
    θ = (r / R) × 360° = (20 / 63.25) × 360° ≈ 113.84° ≈ 114°

3. Step-by-Step Drawing Procedure

  1. Select an apex point O.
  2. With center O and radius R = 63.25 mm, draw a circular arc.
  3. Draw the starting radial generator line OA.
  4. Using a protractor centered at O, measure an angle of θ = 114° from OA and draw the closing radial generator line OA'.
  5. Divide the sector angle of 114° into 8 equal parts (each angle ≈ 14.25°) by radial lines and label them 1, 2, 3, dots, 8, A'.
  6. The resulting circular sector O-A-A' is the complete lateral surface development of the cone.

Q.4 (b)

Question

A circular plate of diameter 50 mm is resting on HP on a point on the circumference with its surface inclined at 45° to HP and perpendicular to VP. Draw its projections.

Solution

1. Given Data

  • Plate shape: Circular disc
  • Diameter (d) = 50 mm
  • Resting on HP on a point of its circumference
  • Surface inclination with HP (θ) = 45°
  • Surface perpendicular to VP

2. Step-by-Step Drawing Procedure

Step 1: Initial Simple Position (Plate parallel to HP)
  1. Draw the reference line X-Y.
  2. In the Top View (below XY), draw a full circle of diameter 50 mm representing the true shape of the plate.
  3. Divide the circle into 8 (or 12) equal parts, labeled a, b, c, d, e, f, g, h.
  4. Project these points vertically upward onto the XY line to get the initial Front View as a horizontal line segment of length 50 mm: a'(e'), where a' is the leftmost point and e' is the rightmost point.
Step 2: Surface Inclined to HP
  1. On the XY line, choose a resting point a'.
  2. Draw a line of length 50 mm passing through a' inclined at an angle of 45° to the XY line.
  3. Transfer all projected points from the initial front view along this line: b', h', c', g', d', f', e'. This line is the final Front View.
  4. From each point on this inclined line, draw vertical projectors downward.
  5. From each corresponding point of the initial circular top view, draw horizontal projectors to intersect the corresponding vertical projectors:
  • Point a lies on the horizontal projector from initial a and vertical projector from tilted a'.
  • Similarly, locate points b, c, d, e, f, g, h.
  1. Join all these intersecting points smoothly using a French curve.
  2. Result: The final Top View is an ellipse having:
  • Major axis = diameter of circle = 50 mm (perpendicular to VP, parallel to XY).
  • Minor axis = 50 cos 45° = 50 × 0.7071 ≈ 35.36 mm.

Q.4 (c)

Question

A cone having base diameter 80mm and height 90mm is resting with its base on H.P.. It is cut by A.I.P. at 45o to the H.P. The cutting plane passes through the midpoint of the axis of the cone. Draw the elevation, the sectional plan and true shape of the section.

Solution

1. Given Data

  • Base diameter (d) = 80 mm implies Base radius (r) = 40 mm
  • Axis height (h) = 90 mm
  • Cutting plane: Auxiliary Inclined Plane (A.I.P.) inclined at 45° to HP, perpendicular to VP.
  • Passes through the midpoint of axis: Height of section point = 90 / 2 = 45 mm above base (HP).

2. Step-by-Step Drawing Procedure

Step 1: Normal Projections of Cone
  1. Draw the XY line.
  2. Top View: Below XY, draw a circle of diameter 80 mm with center o. Divide into 12 equal parts: 1, 2, 3, dots, 12. Join each to center o.
  3. Front View (Elevation): Project the base points to the XY line. Mark apex o' on the axis at a height of 90 mm above XY. Draw an isosceles triangle o'-1'-7' representing the cone elevation.
Step 2: Cutting Plane & Sectional Front View
  1. On the axis o'm', measure 45 mm up from the base to find the axis midpoint K'.
  2. Through K', draw a cutting plane line V-T inclined at 45° to the XY line. Show it with thick ends and thin center long-chain dashes.
  3. The cutting plane cuts the various generators at points p_1', p_2', dots, p_{12}'.
Step 3: Sectional Plan (Top View)
  1. Project the cut points from the front view vertically downward to the corresponding generator lines in the Top View:
  • p_1' on o'-1' implies p_1 on o-1.
  • For generators near the profile (o'-4' and o'-10'), project the cut point horizontally to the extreme generator o'-7', then vertically down to the horizontal center line, and swing an arc centered at o to locate p_4 and p_{10}.
  1. Connect points p_1, p_2, dots, p_{12} with a smooth curve.
  2. Hatch the sectioned region with thin continuous parallel lines inclined at 45°.
Step 4: True Shape of Section
  1. Draw a new reference line X_1-Y_1 parallel to the cutting plane line V-T.
  2. From each cut point p_1', p_2', dots on the cutting plane, draw perpendicular projection lines toward X_1-Y_1.
  3. Transfer distances of points in the top view from the central horizontal axis to both sides of X_1-Y_1.
  4. Join these points with a smooth curve.
  5. Hatch the true shape. The resulting true shape is an ellipse.

Q.4 (a) OR

Question

A square pyramid, base 40 mm side and axis 65 mm long, has its base on the HP and all the edges of the base equally inclined to the VP. It is cut by a section plane, perpendicular to the VP, inclined at 45º to the HP and bisecting the axis. Draw its development.

Solution

1. Given Data

  • Base of pyramid: Square, side = 40 mm
  • Axis length (h) = 65 mm
  • Base on HP, edges equally inclined to VP (i.e., at 45° to XY)
  • Section plane: Perpendicular to VP, inclined at 45° to HP, bisecting the axis (passing at height 65 / 2 = 32.5 mm from base).

2. True Length (TL) of Slant Edge

  • Half-diagonal of the base r = 40 / √(2) ≈ 28.28 mm
  • True slant edge length L = √(h^2 + r^2) = √(65^2 + 28.28^2) = √(4225 + 800) = √(5025) ≈ 70.89 mm ≈ 71 mm

3. Step-by-Step Drawing Procedure

  1. Orthographic Projections:
  • In the Top View, draw a square of side 40 mm with all sides at 45° to XY. Label corners a, b, c, d and apex o.
  • Project to the Front View: Base a'c' lies on the XY line. Apex o' is 65 mm above XY. Slant edges o'b' and o'd' are profile edges, while o'a' and o'c' show the true slant length L = 71 mm.
  1. Section Plane:
  • Mark the axis midpoint at 32.5 mm above XY.
  • Draw the cutting plane line at 45° to the XY line passing through this midpoint.
  • Mark cut points on the slant edges: 1' on o'a', 2' on o'b', 3' on o'c', and 4' on o'd'.
  • Project these points horizontally onto the true-length slant edge (o'a') to read their true distances from apex o (OL_1, OL_2, OL_3, OL_4).
  1. Development of Lateral Surface:
  • Draw an arc with radius L = 71 mm centered at O.
  • Along this arc, step off 4 chords, each of length equal to base side 40 mm: A, B, C, D, A.
  • Join O to A, B, C, D, A with thin straight lines (fold lines).
  • Along generator OA, mark A_1 at true distance OL_1.
  • Along OB, mark B_1 at true distance OL_2.
  • Along OC, mark C_1 at true distance OL_3.
  • Along OD, mark D_1 at true distance OL_4.
  • Along final OA, mark A_1 at true distance OL_1.
  1. Final Outline: Join A_1-B_1-C_1-D_1-A_1 and A-B-C-D-A with thick straight lines to form the developed lateral surface of the truncated pyramid.

Q.4 (b) OR

Question

An isosceles triangular XYZ having its base XY=50 and altitude 60mm is resting on H.P. on is base XY with its surface making and angle of 450 to H.P. Draw projection of plane.

Solution

1. Given Data

  • Plane: Isosceles triangle XYZ
  • Base XY = 50 mm
  • Altitude = 60 mm
  • Resting on HP on base XY
  • Surface inclined at 45° to HP and perpendicular to VP.

2. Step-by-Step Drawing Procedure

Step 1: Initial Position (Surface parallel to HP)
  1. Draw the reference line X-Y.
  2. Top View: Below XY, draw horizontal line xy = 50 mm parallel to XY.
  3. From the midpoint of xy, draw a perpendicular line of length 60 mm downwards to locate apex z.
  4. Join xz and yz to complete the true shape of the isosceles triangle.
  5. Front View: Project x, y to the XY line as x'(y'), and apex z to the XY line as z'. The front view is a single horizontal line segment x'z' of length 60 mm on the XY line.
Step 2: Surface Inclination (Surface tilted 45° to HP)
  1. On the XY line, keep point x'(y') fixed.
  2. Through x'(y'), draw a line segment of length 60 mm inclined at 45° to the XY line to locate apex z'.
  3. This tilted line x'z' is the final Front View.
  4. Final Top View:
  • From x'(y'), project vertically down to meet horizontal projectors from initial x and y. Points x and y remain unchanged in spacing (50 mm apart).
  • From z', project vertically down to meet the horizontal projector from initial z to locate the new apex position z.
  • The apparent altitude in the Top View becomes 60 cos 45° = 60 × 0.7071 ≈ 42.43 mm.
  • Join x, y, and z with thick lines to form the final Top View.

Q.4 (c) OR

Question

A Hexagonal prism is resting on one of its side of base 30mm , such that axis 60mm is inclined at 45º to the HP and the side on which it is resting is inclined at 300 to V.P. Draw the projections.

Solution

1. Given Data

  • Object: Hexagonal Prism
  • Base edge = 30 mm
  • Axis length = 60 mm
  • Resting on HP on one of its base edges
  • Axis inclined at 45° to HP (Stage 2)
  • The resting base edge is inclined at 30° to VP (Stage 3)

2. Step-by-Step Drawing Procedure

Stage 1: Simple Position (Axis perpendicular to HP)
  1. Draw reference line X-Y.
  2. Top View: Draw a regular hexagon of side 30 mm below the XY line such that one edge is perpendicular to the XY line (so that when tilted onto HP, it rests on an edge).
  3. Number base corners 1, 2, 3, 4, 5, 6 and top face corners a, b, c, d, e, f.
  4. Front View: Project all corners vertically up to the XY line. Draw a rectangle of height 60 mm showing the axis vertical and face edges visible.
Stage 2: Axis Inclined at 45° to HP
  1. If the axis is inclined at 45° to HP, the base is inclined at 90° - 45° = 45° to HP.
  2. Tilt the entire Front View so that the resting base edge remains on the XY line and the base makes an angle of 45° with XY.
  3. The axis is now inclined at 45° to HP.
  4. Top View (Stage 2): Project all vertices vertically down from the tilted Front View and horizontally from the Stage 1 Top View. Connect the intersecting points to obtain the intermediate Top View, paying close attention to visible (solid) and hidden (dashed) edges.
Stage 3: Resting Edge Inclined at 30° to VP
  1. In the Top View of Stage 2, identify the resting edge (which lies on the XY line in elevation).
  2. Draw a line inclined at 30° to the XY line below XY.
  3. Reproduce the entire Top View from Stage 2 without altering any dimensions, placing the resting edge along this 30° inclined line.
  4. Final Front View: Project all points vertically upward from this rotated Top View and horizontally across from the Stage 2 Front View.
  5. Connect the corresponding corner points to complete the final Front View. Outline visible boundaries with continuous thick lines and hidden edges with dashed lines.

Q.5 (a)

Question

Explain use of following AUTOCAD commands: (1) MOVE (2) FILLET (3) OFFSET (4) CHAMFER

Solution

1. MOVE Command

  • Purpose: Relocates existing objects from one position to another in the drawing area without altering their size or orientation.
  • Syntax / Shortcut: M or MOVE
  • Working Steps:
  1. Select the objects to move.
  2. Specify a base point (e.g., an endpoint or center).
  3. Specify a second point (displacement destination) or enter relative Cartesian/polar coordinates.

2. FILLET Command

  • Purpose: Rounds and connects two intersecting or non-parallel lines, arcs, or polyline segments with a smooth tangent arc of a specified radius.
  • Syntax / Shortcut: F or FILLET
  • Key Options: Radius (R) to specify the corner curvature; Polyline (P) to fillet an entire 2D polyline at once; Trim (T) to control whether original line ends are trimmed or kept.

3. OFFSET Command

  • Purpose: Creates parallel copies of lines, concentric circles, or parallel polylines at a specified uniform perpendicular distance or through a specified point.
  • Syntax / Shortcut: O or OFFSET
  • Working Steps:
  1. Enter the offset distance.
  2. Select the object to offset.
  3. Click on the side (left/right/inside/outside) where the copy should be placed.

4. CHAMFER Command

  • Purpose: Bevels or creates an angled transitional cut between two intersecting non-parallel lines.
  • Syntax / Shortcut: CHA or CHAMFER
  • Key Options: Distance (D) to specify the cutback distance along each line; Angle (A) to specify a cutback distance on the first line and a chamfer angle for the second.

Q.5 (b)

Question

Draw isometric drawing for the Figure-1.

Solution

1. Analysis of Figure-1 Geometry

Based on Figure-1, the object is a stepped bracket/block characterized by:

  • Overall length (X-axis): 75 mm
  • Overall width (Y-axis): 50 mm
  • Overall height (Z-axis): 50 mm
  • Features include:
  1. A base plate of size 75 mm × 50 mm with thickness 15 mm.
  2. An upright vertical wall/flange at one end of thickness 15 mm rising to the full height of 50 mm.
  3. A central circular hole or semi-circular cutout of diameter 20 mm on the horizontal base, or a triangular supporting rib connecting the upright flange to the base plate.

2. Step-by-Step Isometric Drawing Procedure

  1. Establish Isometric Axes:
  • Draw a horizontal reference line.
  • Choose an origin point O.
  • Draw three isometric axes: one vertical (90°), one inclined at 30° to the right, and one inclined at 30° to the left.
  1. Construct the Enclosing Isometric Box:
  • Along the 30° right axis, measure overall length = 75 mm.
  • Along the 30° left axis, measure overall width = 50 mm.
  • Along the vertical axis, measure overall height = 50 mm.
  • Complete the bounding isometric box using faint (construction) lines.
  1. Block-out Major Profiles:
  • From the bottom corners, measure 15 mm vertically up to establish the top plane of the base plate.
  • Along the length axis, measure 15 mm from the rear upright wall to mark the thickness of the vertical column.
  1. Draw Cutouts and Webs:
  • Locate the center of any specified circular cutout on the base surface.
  • Construct an isometric square (rhombus) with side equal to the diameter (20 mm) and draw the ellipse using the standard four-center method.
  • If a triangular rib exists, locate its starting points on the upright face and base plate and connect them with straight lines.
  1. Finishing:
  • Darken all visible object outlines with thick continuous lines.
  • Erase or retain faint construction lines.
  • Ensure hidden edges are omitted as per standard isometric drawing conventions.

Q.5 (a) OR

Question

Discuss advantages of AUTOCAD over conventional drawing.

Solution

Overview

Computer-Aided Design (AutoCAD) has largely replaced traditional manual drafting boards due to significant improvements in drafting productivity, quality, and workflow integration.

Major Advantages

  1. High Accuracy and Precision:
  • Manual drawings suffer from human physical errors, pencil width variations, and scale inaccuracies.
  • AutoCAD provides mathematical precision up to 16 decimal places, eliminating cumulative drawing errors.
  1. Speed and Time Savings:
  • Repetitive drawing tasks are automated using commands such as COPY, ARRAY, MIRROR, and BLOCK.
  • Standard engineering components (bolts, nuts, bearings) can be inserted instantly from pre-existing digital libraries.
  1. Ease of Editing and Modification:
  • Design revisions in conventional drawing often require erasing and redrawing entire sheets.
  • In AutoCAD, changes are made instantly using STRETCH, TRIM, EXTEND, and SCALE without damaging the drawing surface.
  1. Layer Management:
  • Drawings can be organized onto distinct layers (e.g., outlines, hidden lines, dimensions, centerlines, hatching).
  • Layers can be isolated, frozen, locked, or color-coded for improved clarity and error detection.
  1. Storage, Portability, and Collaboration:
  • Physical drawings require large physical storage space and degrade over time.
  • CAD files (.dwg, .dxf) are compact, can be stored in the cloud, shared instantly worldwide, and integrated directly into Computer-Aided Manufacturing (CAM) systems.

Q.5 (b) OR

Question

Draw the following views for Figure-2 using first angle projection method. (1) Sectional Elevation along A-B from X (2) Top view

Solution

1. Component Geometry Analysis (Figure-2)

Based on Figure-2, the component is a cast support bracket:

  • Overall Dimensions: Length = 80 mm, Width = 50 mm, Height = 60 mm.
  • Features:
  • A horizontal base plate of thickness 12 mm.
  • A central vertical cylindrical boss or hollow upright collar with outer diameter 40 mm and an inner concentric through-hole of diameter 20 mm.
  • A cutting plane A-B passing longitudinally through the center of the cylindrical boss and base plate viewed along arrow X.

2. Step-by-Step Drawing Procedure (First Angle Projection)

In First Angle Projection, the Sectional Front View (Elevation) is placed directly above the Top View.

(1) Sectional Elevation along A-B from X
  1. Draw the reference line X-Y.
  2. Draw the outline of the base plate: length 80 mm, height 12 mm.
  3. Draw the vertical upright feature at the center: width equal to outer diameter 40 mm, extending up to total height 60 mm.
  4. Show the central hole of diameter 20 mm passing vertically through the boss and base: since cutting plane A-B cuts directly through this axis, the hole becomes visible as solid lines (not hidden dashed lines).
  5. Apply section hatching (thin parallel continuous lines inclined at 45°) to all solid material sliced by the cutting plane (the left and right solid walls of the cylinder and the base).
  6. The open hole area remains unhatched.
(2) Top View
  1. Project vertically downward from the Sectional Elevation to below the XY line.
  2. Draw the boundary rectangle of the base: length 80 mm, width 50 mm.
  3. Locate the center of the cylindrical feature at the intersection of centerlines.
  4. Draw the concentric circles:
  • Outer circle: diameter 40 mm (solid visible line).
  • Inner through-hole: diameter 20 mm (solid visible line).
  1. Draw the cutting plane line A-B along the longitudinal centerline, with thick ends, arrows pointing in direction X, and labeled 'A' and 'B'.
  2. Add all essential dimensions (80, 50, 60, Ø40, Ø20, 12 mm) in the aligned system.

Frequently Asked Questions

Why is the top view drawn below the front view in first angle projection?

In first angle projection, the object is placed in the first quadrant, situated between the observer and the projection planes. When the observer views the object from above, the projection is cast downward onto the horizontal plane. When the horizontal plane is rotated 90 degrees downward to align with the vertical plane, it swings below the XY line, positioning the top view below the front view.

How can I verify if my line projection construction is correct?

A foolproof check in straight-line orthographic projections is that the final elevation point (b') and final plan point (b) must always lie on the exact same vertical projector line perpendicular to the reference line XY.

What is the four-center method used for in isometric drawings?

In isometric projection, a circle appears as an ellipse. The four-center method is an approximate geometric construction technique that uses four circular arc centers located on the diagonals and perpendicular bisectors of an isometric square (rhombus) to draw smooth ellipses accurately without needing a French curve.

GTU Basic Electronics (3110016) Semester 1 & 2 Winter 2025 Solved Paper

Complete, student-friendly worked solutions for Gujarat Technological University (GTU) Basic Electronics (3110016) Winter 2025 examination with circuit diagrams, waveforms, and clear explanations.

Introduction

This document provides step-by-step worked solutions for the GTU Winter 2025 examination in Basic Electronics (Subject Code: 3110016). Prepared strictly according to the official GTU question paper, every solution incorporates clear theory, labeled circuit diagrams, characteristic curves, mathematical expressions, and comparative tables tailored to match the allotted marks.

Paper Information

University
Gujarat Technological University
Department
First Year Engineering
Semester
Semester 1 & 2
Subject
Basic Electronics
Subject Code
3110016
Exam
Winter 2025
Year
2025

Questions and Solutions

Q.1 (a)

Question

Draw the vi characteristics for ideal diode and real diode.

Solution

V-I Characteristics of Ideal Diode vs Real Diode

A diode is a two-terminal semiconductor device that allows current to flow primarily in one direction.

1. Ideal Diode Characteristics
  • In Forward Bias (V > 0): Acts as an ideal closed switch (zero resistance, zero threshold voltage, voltage drop = 0 V).
  • In Reverse Bias (V < 0): Acts as an ideal open switch (infinite resistance, zero leakage current, current I = 0 A).
2. Real (Practical) Diode Characteristics
  • In Forward Bias: Current remains nearly zero until the applied voltage reaches the cut-in (knee) voltage (approximately 0.7 V for Silicon and 0.3 V for Germanium). Beyond this voltage, current increases exponentially.
  • In Reverse Bias: A very small reverse saturation current (Is in microamperes or nanoamperes) flows due to minority charge carriers. At a sufficiently high reverse voltage (Breakdown Voltage, Vbr), the diode enters breakdown and current rises abruptly.
Ideal Diode V-I Curve:               Real Diode V-I Curve:

         I (Current)                         I (mA)
             |                                   |         /
             | (Conducts at V=0)                 |        / (Exponential)
             |                                   |       / 
   ----------+--------> V              ----------+------/-----> V (Volts)
   (Blocks   |                 -Vbr              |    V_gamma (0.7V for Si)
    V < 0)   |                   |               |
             |                   +---------------+ (Reverse Saturation Is)
                                 |                 
                                 | (Breakdown)     

(Schematic, not to scale)

Q.1 (b)

Question

Explain the forward and reverse bias of PN junction.

Solution

Forward and Reverse Bias of a PN Junction

A PN junction is formed by joining p-type and n-type semiconductor materials. The behavior of the junction depends strongly on the polarity of an external DC voltage applied across it.

1. Forward Biasing
  • Connection: The positive terminal of the external DC source is connected to the p-type region, and the negative terminal is connected to the n-type region.
  • Working Mechanism:
  1. The applied positive potential repels holes from the p-side toward the junction, while the negative potential repels free electrons from the n-side toward the junction.
  2. This opposes and reduces the internal barrier potential (built-in electric field).
  3. The width of the depletion layer decreases significantly.
  4. Once the applied voltage exceeds the cut-in voltage (0.7 V for Si, 0.3 V for Ge), majority carriers cross the junction in large numbers, resulting in a large forward current flowing from p to n.
2. Reverse Biasing
  • Connection: The positive terminal of the external DC supply is connected to the n-type region, and the negative terminal is connected to the p-type region.
  • Working Mechanism:
  1. The external positive terminal attracts electrons away from the junction on the n-side, and the negative terminal attracts holes away from the junction on the p-side.
  2. This widens the depletion layer and reinforces the internal barrier potential.
  3. Majority carriers cannot cross the barrier; junction resistance becomes extremely high.
  4. Only a very small current (in the range of nanoamperes for silicon), called the Reverse Saturation Current (Is), flows due to thermally generated minority carriers.
Forward Bias:                         Reverse Bias:
   [ p-type | n-type ]                   [ p-type | n-type ]
      |        |                            |        |
     (+)      (-)                          (-)      (+)
 (Depletion layer narrows)            (Depletion layer widens)

Q.1 (c)

Question

Discuss the operation of full bridge rectifier circuits with voltage and current waveforms.

Solution

Operation of Full Wave Bridge Rectifier

A bridge rectifier converts alternating current (AC) into unidirectional direct current (DC) using four diodes connected in a closed bridge configuration, without requiring a center-tapped transformer.

1. Circuit Diagram
                  D1          D2
          +------|>|----+----|<|------+
          |             |             |
  AC      |             |             |    +
Input ----+             RL (Load)     +---( Vo )
Secondary |             |             |    -
          |             |             |
          +------|<|----+----|>|------+
                  D4          D3

(Schematic, not to scale)

2. Circuit Operation
  • During the Positive Half-Cycle of AC Input:
  • The upper terminal of the secondary winding is positive with respect to the lower terminal.
  • Diodes D1 and D3 are forward biased (conducting).
  • Diodes D2 and D4 are reverse biased (non-conducting, acting as open switches).
  • Current path: Secondary (+) -> D1 -> Load Resistor (RL, top to bottom) -> D3 -> Secondary (-).
  • Output voltage appears across RL with the top terminal positive.
  • During the Negative Half-Cycle of AC Input:
  • The upper terminal of the secondary winding becomes negative, and the lower terminal becomes positive.
  • Diodes D2 and D4 become forward biased (conducting).
  • Diodes D1 and D3 become reverse biased.
  • Current path: Secondary (-) [lower] -> D2 -> Load Resistor (RL, top to bottom) -> D4 -> Secondary (+) [upper].
  • Current passes through the load RL in the exact same direction as during the positive half-cycle.
3. Voltage and Current Waveforms
AC Input Voltage (Vin):
   Vin ^     +----+            +----+
       |    /      \          /      \
     0 +---+--------\--------+--------\-----> omega*t
       |             \      /          \    /
       |              +----+            +--+

Output Voltage across RL (Vo) and Load Current (IL):
   Vo  ^
       |    +----+    +----+    +----+    +----+
       |   /      \  /      \  /      \  /      \
     0 +--+--------++--------++--------++--------+--> omega*t
          Conduction: Conduction: Conduction: Conduction:
          (D1, D3)    (D2, D4)    (D1, D3)    (D2, D4)

(Schematic, not to scale)

4. Key Performance Parameters
  • Peak Inverse Voltage (PIV): PIV = Vm (where Vm is peak secondary voltage).
  • Rectification Efficiency (eta): eta = 81.2%.
  • Ripple Factor (gamma): gamma = 0.482.
  • Fundamental Ripple Frequency: fripple = 2 * fin (e.g., 100 Hz for a 50 Hz line supply).

Q.2 (a)

Question

Draw the circuits for clipping the voltage waveforms.

Solution

Circuits for Clipping Voltage Waveforms

Clipping circuits (clippers) remove or truncate unwanted portions of an input signal above or below a chosen reference level without distorting the remaining part of the waveform.

1. Positive Diode Clipper

Removes the positive half-cycle of the input voltage.

        R
  o----/\/\/\-----+--------o Output (Vo)
                  | 
                 --- 
                 / \ Diode (D)
                 --- 
                  | 
  o---------------+--------o

(Output retains only negative half-cycles; positive half-cycles are clipped at ~0 V).

2. Negative Diode Clipper

Removes the negative half-cycle of the input voltage.

        R
  o----/\/\/\-----+--------o Output (Vo)
                  | 
                 --- 
                 \ / Diode (D)
                 --- 
                  | 
  o---------------+--------o

(Output retains only positive half-cycles; negative half-cycles are clipped at ~0 V).

3. Biased Clipper (Combination / Two-level Clipper)

Clips both positive and negative peaks at predetermined DC reference voltages (V1 and V2).

           R
  Vin o---/\/\/\-----+-----------------+---o Vo
                     |                 | 
                    --- D1            --- D2
                    / \               \ / 
                    ---               --- 
                     |                 | 
                    --- +             --- -
                   ---  V1           ---  V2
                    | -               | +
  -------------------+-----------------+---

(Schematics, not to scale)

Q.2 (b)

Question

Explain the characteristics of Zener diode.

Solution

Characteristics of a Zener Diode

A Zener diode is a heavily doped silicon PN junction diode designed specifically to operate safely in the reverse breakdown region without damage.

1. Operating Regions & Characteristics
                      I_forward (mA)
                            ^
                            |         /
                            |        / Forward region
                            |       /  (V_gamma ~ 0.7V)
  -Vz                       |      /
<--+------------------------+-----+--------> V_reverse
   |                        |   0.7V
   |                        |  I_reverse (microamps)
   |                        |
   | (Breakdown             |
   |  Region)               |
   |                        |
   v                        |
  I_zmax                    v

(Schematic, not to scale)

  • Forward Bias Region: Behaves identical to a normal silicon PN junction diode. Conduction begins once forward voltage exceeds cut-in voltage (~0.7 V).
  • Reverse Bias Region (Before Breakdown): Shows a very small reverse leakage current until the reverse breakdown voltage (Vz) is reached.
  • Reverse Breakdown Region (Zener Region):
  • When reverse voltage reaches Vz, the junction undergoes breakdown (via Zener breakdown for heavily doped junctions with Vz < 5-6 V, or Avalanche breakdown for higher voltages).
  • Current increases sharply from a minimum knee current (Izmin) up to a maximum rated current (Izmax).
  • Over this entire wide range of current, the voltage across the diode remains practically constant at Vz.
2. Primary Application

Because it maintains a constant voltage despite wide variations in load current or unregulated input voltage, the Zener diode is universally utilized as a shunt voltage regulator.

Q.2 (c)

Question

Write short not on bipolar junction transistor (BJT).

Solution

Short Note on Bipolar Junction Transistor (BJT)

A Bipolar Junction Transistor (BJT) is a three-terminal, two-junction semiconductor device used for amplification and switching. It is called bipolar because operation relies on both charge carriers: electrons and holes.

1. Structure and Types

A BJT consists of three distinctly doped regions forming two back-to-back PN junctions:

  • NPN Transistor: A thin p-type base sandwiched between two n-type regions (majority carriers in the device are electrons).
  • PNP Transistor: A thin n-type base sandwiched between two p-type regions (majority carriers are holes).
       NPN Transistor                      PNP Transistor
             C                                   C
             |                                   |
          +--+--+                             +--+--+
          |  |  |                             |  |  |
     B ---|  v  |                        B ---|  ^  |  (Arrow on emitter
          +--+--+                             +--+--+   shows conventional
             |                                   |      current direction)
             E                                   E

(Schematic, not to scale)

2. Three Distinct Regions
  • Emitter (E): Heavily doped; medium physical size; function is to emit majority carriers into the base.
  • Base (B): Extremely thin and very lightly doped; allows almost all injected carriers to diffuse into the collector.
  • Collector (C): Moderately doped; physically the largest region to effectively dissipate heat generated by collecting carriers.
3. Junctions and Operating Modes
  • Emitter-Base Junction (EBJ)
  • Collector-Base Junction (CBJ)

| Mode of Operation | EBJ Biasing | CBJ Biasing | Primary Application | |---|---|---|---| | Cut-off | Reverse | Reverse | Open Switch (OFF state) | | Active | Forward | Reverse | Linear Signal Amplifier | | Saturation | Forward | Forward | Closed Switch (ON state) | | Inverted | Reverse | Forward | Rarely used (attenuator) |

4. Basic Current Relationship

By Kirchhoff's Current Law: IE = IB + IC Since the base is very thin and lightly doped, IB is very small (1% to 5% of IE), meaning IC ≈ IE.

5. Common Configurations

BJTs can be connected in three standard circuit configurations:

  1. Common Emitter (CE) – High voltage and current gain (most popular for amplifiers).
  2. Common Base (CB) – Low input impedance, high output impedance, unity current gain.
  3. Common Collector (CC) – High input impedance, low output impedance (buffer/emitter follower).

Q.2 (c) OR

Question

Explain the operation of transistor as amplifier in Common Emitter(CE) configuration.

Solution

Operation of Transistor as an Amplifier in Common Emitter (CE) Configuration

In the Common Emitter (CE) configuration, the emitter terminal is common to both the input and output circuits. It is the most widely used amplifier configuration due to its ability to provide high current gain, high voltage gain, and large power gain.

1. Circuit Diagram
                   +Vcc
                    |
                    | Rc
                    +---/\/\/\----+----> Vo (Amplified Output)
                    |             |
             C1     |  C        ----- C2
     Vin o---||----+---| BJT    ----- 
             |     |   E          |
             /     \    |       Load
          R1 \  R2 /    | 
             /     \    +---------+ 
             |     |    |         | 
            ===   ===   \ RE    ----- CE
            GND   GND   /       ----- 
                        \         |
                        +---------+
                        |
                       === GND

(Schematic, not to scale)

2. Biasing and Circuit Components
  • Q-point Biasing: Resistors R1, R2, and RE set up the DC operating point in the active region such that the Base-Emitter junction is forward biased (VBE ≈ 0.7 V) and the Collector-Base junction is reverse biased.
  • Coupling Capacitors (C1, C2): Block DC bias currents from passing to the source or load, while allowing the AC signal to pass through unattenuated.
  • Bypass Capacitor (CE): Provides a very low impedance path to ground for AC signal currents, preventing degeneration across RE and keeping the AC voltage gain high.
3. Working Principle and Amplification Mechanism
  1. Without AC input: A steady DC collector current ICQ flows through load resistor Rc, giving a steady DC collector-to-emitter output voltage:
    VCE = VCC - IC * Rc
  2. With AC input applied: The small alternating input signal vin superimposes on the DC base-emitter voltage VBE.
  3. Positive Half-Cycle of Vin:
  • Total vBE increases (VBE + vin).
  • Base current iB increases.
  • By transistor action, collector current increases by a much larger factor: ic = beta * ib.
  • The increased current causes a larger voltage drop across Rc (ic * Rc).
  • Therefore, output voltage vCE = VCC - (IC + ic) * Rc decreases.
  1. Negative Half-Cycle of Vin:
  • Total vBE decreases, causing iB and iC to decrease.
  • The voltage drop across Rc decreases, causing the output voltage vCE to increase.
4. Phase Reversal

A unique and defining property of the CE amplifier is that the output voltage is 180° out of phase with respect to the input voltage.

5. Voltage Gain Expression

Voltage gain is defined as: Av = vo / vin = - (beta Rc') / r_in

(where the negative sign signifies the 180° phase inversion).*

Q.3 (a)

Question

Write key factors to achieve faithful amplifications.

Solution

Key Factors to Achieve Faithful Amplification

Faithful amplification means increasing the amplitude of an input AC signal without introducing any distortion or change in its waveform shape.

To ensure faithful amplification, three conditions must be strictly satisfied at all times during the signal cycle:

  1. Proper Minimum Base-Emitter Voltage (Forward Bias of EBJ):
    The forward bias across the base-emitter junction must not fall below the cut-in voltage (0.7 V for Silicon, 0.3 V for Germanium) at any point during the negative peak of the AC input signal. Otherwise, the transistor enters the cut-off region, clipping the output waveform.
  1. Adequate Minimum Collector-Emitter Voltage (VCE > VCE(sat)):
    The collector-to-emitter voltage must remain greater than the saturation voltage (typically 0.2 V for Silicon) at any point during the positive peak of the AC input signal. If VCE drops below VCE(sat), the transistor enters the saturation region, flattening the output waveform.
  1. Proper Collector Current (IC > 0):
    A sufficient quiescent collector current ICQ must flow so that even during the most negative excursion of the input signal, the transistor remains completely within the active linear operating region.

Q.3 (b)

Question

Discuss the importances of operating points in transistor.

Solution

Importance of the Operating Point (Q-Point) in a Transistor

The operating point, commonly called the Quiescent point (Q-point), is the specific DC bias state of a transistor characterized by DC values (VCEQ, ICQ) in the absence of an applied AC input signal.

Importance and Significance
  1. Ensures Operation in Active Linear Region:
    For faithful linear amplification, the transistor must remain in the active region at all times. Setting an accurate Q-point prevents the signal from crossing into saturation (where the output is clipped at the bottom) or cut-off (where the output is clipped at the top).
  1. Maximizes Symmetrical Peak-to-Peak Output Swing:
    Positioning the Q-point precisely in the middle of the DC load line (VCEQ = VCC / 2) allows maximum unclipped signal voltage excursion in both positive and negative directions.
  1. Thermal Stability and Prevention of Thermal Runaway:
    Transistor parameters (reverse leakage current ICBO, base-emitter voltage VBE, and current gain beta) are highly sensitive to temperature:
  • ICBO doubles approximately every 10 °C rise.
  • Increased ICBO causes an increase in total IC, raising internal junction temperature (P = VCE * IC).
  • This cumulative heating can trigger thermal runaway, permanently destroying the transistor.
    A well-stabilized operating point prevents this destructive cycle and keeps the amplifier stable over varying ambient temperatures.

Q.3 (c)

Question

Discuss the load line analysis of transistor.

Solution

Load Line Analysis of a Transistor

Load line analysis is a graphical technique used to determine the exact DC operating point (Q-point) and analyze transistor operation under dynamic AC signal conditions on the output characteristic curves.

1. Derivation of DC Load Line Equation

Consider a Common Emitter circuit with collector resistor Rc connected to supply VCC. Applying Kirchhoff’s Voltage Law (KVL) around the collector-emitter output loop:

VCC - IC Rc - VCE = 0 Rearranging for collector current IC: IC = - (1 / Rc)

VCE + (VCC / Rc)

This is a straight-line equation of the form y = mx + c, where:

  • Vertical axis variable y = IC
  • Horizontal axis variable x = VCE
  • Slope m = -1 / Rc
  • Y-intercept c = VCC / Rc
2. Determining the End Points of the DC Load Line
  • Point A (Saturation Point on Y-axis):
    Set VCE = 0:
    IC(sat) = VCC / Rc
    Coordinates: (0, VCC / Rc)
  • Point B (Cut-off Point on X-axis):
    Set IC = 0:
    VCE(off) = VCC
    Coordinates: (VCC, 0)

Connecting these two terminal points on the Common Emitter output characteristic curves forms the DC Load Line.

3. Graphical Representation and Operating Point (Q-Point)
     IC (mA) ^
  Vcc/Rc  A  +
             | \ 
             |   \  IB = 40 microA
             |-----\------------------- 
             |      \   Q (VCEQ, ICQ)
             |-------\----------------- IB = 30 microA (Base Bias)
             |         \ 
             |           \  IB = 10 microA
             |             \ 
           0 +---------------+---------+------> VCE (Volts)
                           VCEQ        B (Vcc)

(Schematic, not to scale)

  • Q-Point Location: The intersection of the DC load line with the specific base current curve IB chosen by the base bias circuit defines the Quiescent Operating Point Q (VCEQ, ICQ).
4. AC Load Line

When an AC signal is applied and an external AC load RL is coupled via a capacitor:

  • Total effective AC collector load becomes rac = Rc || RL.
  • Since rac < Rc, the AC load line has a steeper slope (-1 / rac) passing through the same quiescent point Q.
  • The AC load line determines the maximum unclipped dynamic AC signal limits.

Q.3 (a) OR

Question

What is a stability factor?

Solution

Stability Factor in Transistors

The stability factor S measures how sensitive the collector current IC is to changes in internal, temperature-dependent transistor parameters.

1. Definition and Mathematical Expression

Primarily, the stability factor S is defined as the rate of change of collector current IC with respect to the reverse saturation current ICBO, keeping base-emitter voltage VBE and current gain beta constant:

S = (d IC) / (d ICBO) | (VBE, beta = constant)

General formula for stability factor in a biased BJT: S = (1 + beta) / [ 1 - beta * (d IB / d IC) ]

2. Significance
  • An ideal circuit would have S = 1, meaning variations in leakage current do not get magnified.
  • A smaller numerical value of S indicates superior bias stability against temperature fluctuations.
3. Other Stability Factors

Because temperature also affects VBE and beta, two additional stability factors are defined:

  • S' = (d IC) / (d VBE) (sensitivity to base-emitter cut-in voltage)
  • S'' = (d IC) / (d beta) (sensitivity to transistor current gain)

Q.3 (b) OR

Question

Explain the voltage divider biasing.

Solution

Voltage Divider Biasing

Voltage divider biasing (also called potential divider or universal bias) is the most widely adopted biasing technique because it makes the transistor operating point (Q-point) practically independent of transistor current gain (beta) and ambient temperature.

1. Circuit Diagram
                   +Vcc
                    |
             +------+------+
             |             |
             / R1          / Rc
             \             \
             /             /
             |       C     |
             +-----------|/ BJT
             |         B |\
             / R2          \ E
             \             |
             /             / RE
             |             \
             +------+------+
                    |
                   === GND

(Schematic, not to scale)

2. Circuit Analysis

Resistors R1 and R2 form a voltage divider across supply VCC.

  • Base Voltage (VB):
    If the divider current through R1 and R2 is chosen much larger than the base current IB (I_divider >> IB):
    VB = VCC * [ R2 / (R1 + R2) ]
  • Emitter Voltage (VE):
    VE = VB - VBE
  • Emitter Current (IE):
    IE = VE / RE = (VB - VBE) / RE
  • Collector Current (IC):
    Since IC ≈ IE:
    IC ≈ (VB - VBE) / RE
  • Collector-to-Emitter Voltage (VCE):
    Applying KVL around the output loop:
    VCE = VCC - IC Rc - IE RE ≈ VCC - IC * (Rc + RE)
3. Why It Provides Excellent Stability

Notice that the expression for IC does not contain the parameter beta. Since VB is determined strictly by stable external resistors R1 and R2, and VBE (0.7 V) is negligible compared to VB, the collector current IC remains rock solid against temperature changes and unit-to-unit transistor variations.

Q.3 (c) OR

Question

Discuss the construction and operation of Schottky diode.

Solution

Schottky Diode: Construction and Operation

A Schottky diode (named after Walter H. Schottky) is a unipolar, majority-carrier semiconductor diode characterized by an ultra-fast switching speed and a low forward voltage drop.

1. Construction

Unlike standard PN junction diodes that interface two semiconductors, a Schottky diode is fabricated by forming a direct contact between a metal (such as platinum, tungsten, gold, or molybdenum) and an n-type semiconductor (typically silicon).

                  Metal-Semiconductor Junction
            Anode             |
           (Metal)            |       n-type Silicon (Cathode)
       +---------------+      |      +------------------------+
  o----| Platinum / Al |=============|   n-type Epitaxial     |----o
       +---------------+      |      +------------------------+
                              |      (Heavily doped n+ Substrate)

(Schematic, not to scale)

  • Metal Layer: Acts as the Anode.
  • N-type Silicon: Acts as the Cathode.
  • This metal-semiconductor boundary creates a rectifying contact called a Schottky Barrier.
2. Working Principle and Operation
  • Unbiased Condition:
    The conduction band electrons in the n-type semiconductor have higher average thermal energy than the electrons in the metal. When joined, electrons from the n-side flow into the metal until electrostatic equilibrium is achieved, leaving behind positive uncompensated donor ions in the n-region and building a depletion barrier across the interface.
  • Forward Biasing:
    Applying a positive voltage to the metal relative to the n-type semiconductor lowers the built-in barrier. Electrons in the n-region easily cross into the metal, giving rise to forward current.
  • Key Feature: The forward knee voltage is very low—typically 0.2 V to 0.3 V (compared to 0.7 V for a conventional silicon PN junction).
  • Reverse Biasing:
    Applying a negative voltage to the metal raises the barrier height. Free electrons cannot cross the barrier, resulting in a small reverse leakage current.
3. Major Advantages
  1. Zero Minority-Carrier Storage Time: Because conduction is entirely due to majority carriers (electrons), there are no minority carriers to recombine when switching off. The reverse recovery time trr is negligible (in picoseconds).
  2. Low Forward Conduction Loss: Due to the smaller cut-in voltage (0.2–0.3 V).
4. Applications
  • High-frequency RF mixers and detectors.
  • High-efficiency Switched-Mode Power Supplies (SMPS).
  • Clamping diodes in high-speed digital logic (Schottky TTL).

Q.4 (a)

Question

What are the roles of coupling capacitor and bypass capacitor in amplifier circuits?

Solution

Roles of Coupling Capacitor and Bypass Capacitor in Amplifier Circuits

Capacitors present frequency-dependent impedance given by Xc = 1 / (2 pi f * C). For DC (f = 0 Hz), impedance is infinite (open circuit); for AC signals, impedance is small.

1. Role of Coupling Capacitor (Cin and Cout)
  • DC Isolation: Blocks DC voltages from passing between adjacent stages or from the input source / output load into the transistor base and collector.
  • Preserves Bias Points: Prevents external source resistance or load resistance from altering the transistor's DC operating point (Q-point).
  • AC Signal Transmission: Provides a low-impedance path to couple the alternating input signal into the base and the amplified AC output signal to the load.
2. Role of Emitter Bypass Capacitor (C_E)
  • AC Grounding: Placed in parallel with the emitter resistor RE. For AC signal frequencies, its capacitive reactance is negligible (Xc << RE), effectively shorting AC signals straight to ground.
  • Prevents AC Negative Feedback: Without CE, the AC current flowing through RE develops an opposing AC voltage (ic * RE), which reduces the effective base-emitter signal drive (negative feedback).
  • Maximizes AC Voltage Gain: By bypassing RE for AC signals, the full signal drop appears across the base-emitter junction, maintaining maximum voltage gain.

Q.4 (b)

Question

Discuss the operation of common collector circuits analysis.

Solution

Operation and Analysis of Common Collector (CC) Circuit

The Common Collector circuit, universally known as the Emitter Follower, has its collector terminal connected to AC ground, using the base as input and taking output from the emitter.

1. Circuit Schematic
                  +Vcc
                   |
                   +---------------+ (Collector at AC ground)
                   |               |
                  / R1             |
                  \                |
                  /            C |/ 
      Vin o--||---+------------|    BJT
                  |            B |\ 
                  / R2             \ E
                  \                |
                  /                +---||----> Vo (Output)
                  |                |
                 ===              / RE
                 GND              \ 
                                  / 
                                   |
                                  === GND

(Schematic, not to scale)

2. Circuit Analysis
  • Voltage Gain (Av):
    Applying KVL around the input-output loop:
    vin = ib hie + ie RE
    vo = ie RE = (1 + beta) ib * RE
    Therefore:
    Av = vo / vin = [ (1 + beta) RE ] / [ hie + (1 + beta) RE ]
    Since (1 + beta) * RE >> hie, the voltage gain is:
    Av ≈ 1 (typically between 0.95 and 0.99, slightly less than unity).
  • Phase Relationship:
    The output voltage at the emitter follows the input signal in both amplitude and phase (0° phase shift, hence called the Emitter Follower).
  • Input Impedance (Zin):
    Zin = R1 || R2 || [ hie + (1 + beta) * RE ]
    The input impedance is very high (hundreds of kilo-ohms).
  • Output Impedance (Zout):
    Zout = RE || [ (Rs + hie) / (1 + beta) ]
    The output impedance is very low (tens of ohms).
3. Primary Application

Due to high input impedance and low output impedance, it is extensively used as a buffer amplifier for impedance matching between a high-impedance source and a low-impedance load.

Q.4 (c)

Question

Shows parametric comparisons between of CE, CB and CC.

Solution

Parametric Comparison Between CE, CB, and CC Configurations

The table below summarizes the key operational characteristics and AC parameters of BJT amplifier configurations:

| Parameter / Feature | Common Base (CB) | Common Emitter (CE) | Common Collector (CC) | |---|---|---|---| | Common Terminal | Base | Emitter | Collector | | Input Terminal | Emitter | Base | Base | | Output Terminal | Collector | Collector | Emitter | | Input Impedance (Zin) | Very Low (~ 20 to 50 ohms) | Medium (~ 1 to 2 k-ohms) | Very High (~ 100 to 500 k-ohms) | | Output Impedance (Zout) | Very High (~ 1 M-ohm) | Moderate (~ 50 k-ohms) | Very Low (~ 20 to 100 ohms) | | Current Gain | Less than unity (alpha < 1) | High (beta ≈ 50 to 300) | High (gamma = 1 + beta) | | Voltage Gain | High | High | Approximately unity (< 1) | | Power Gain | Moderate | Highest | Low to Moderate | | Phase Shift (Input to Output) | 0° (In-phase) | 180° (Out-of-phase) | 0° (In-phase) | | Primary Application | High-frequency RF circuits | General audio/voltage amplifiers | Buffer and impedance matching |

Q.4 (a) OR

Question

Draw the circuits of seven segment LED display.

Solution

Seven Segment LED Display Circuit

A seven-segment display consists of seven individual light-emitting diodes arranged in a figure-8 pattern (labeled a through g), plus an optional decimal point (dp).

1. Segment Arrangement
       -- a --
     |         |
     f         b
     |         |
       -- g --
     |         |
     e         c
     |         |
       -- d --    * dp
2. Circuit Configurations (Common Anode and Common Cathode)
Common Cathode (CC) Configuration:        Common Anode (CA) Configuration:

        a  b  c  d  e  f  g                     +Vcc (Common)
        |  |  |  |  |  |  |                           |
        v  v  v  v  v  v  v                           +-------+
       --- --- --- --- --- ---                        |       |
        |  |  |  |  |  |  |                          ---     ---
        +--+--+--+--+--+--+                          / \     / \
                 |                                  --+--   --+--
                === GND                               |       |
     (Active HIGH inputs:                           R /     R /
      Logic 1 turns segment ON)                     \       \ 
                                                      |       |
                                                      a       b  ... (inputs)
                                            (Active LOW inputs:
                                             Logic 0 turns segment ON)

(Schematic, not to scale)

Q.4 (b) OR

Question

What are the differences between FET and BJT?

Solution

Differences Between FET and BJT

| Parameter / Feature | Bipolar Junction Transistor (BJT) | Field Effect Transistor (FET) | |---|---|---| | Full Form | Bipolar Junction Transistor | Field Effect Transistor | | Carrier Action | Bipolar: Conduction involves both electrons and holes. | Unipolar: Conduction involves only majority carriers (electrons or holes). | | Control Type | Current-controlled device (output IC depends on input IB). | Voltage-controlled device (output ID depends on input VGS). | | Input Impedance | Low to moderate (~ a few kilo-ohms). | Extremely high (~ 10^8 to 10^14 ohms) due to reverse-biased gate or insulating oxide. | | Terminals | Base (B), Emitter (E), Collector (C). | Gate (G), Source (S), Drain (D). | | Noise Performance | Higher noise level. | Much lower electrical noise (ideal for input stages). | | Thermal Stability | Negative temperature coefficient (prone to thermal runaway). | Positive temperature coefficient (immune to thermal runaway). | | Fabrication Size | Relatively large silicon area. | Extremely small and compact; highly suitable for VLSI / IC design. | | Offset Voltage | Has small collector-emitter offset voltage in saturation. | No offset voltage across drain and source. |

Q.4 (c) OR

Question

Write short note on MOSFET.

Solution

Short Note on MOSFET

A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a unipolar, voltage-controlled four-terminal device (Drain, Source, Gate, and Body/Substrate) where the gate is electrically insulated from the conducting channel by a thin layer of silicon dioxide (SiO2).

1. Classification of MOSFETs
  • Depletion-type MOSFET (D-MOSFET): A physical channel exists at zero gate bias (VGS = 0). It can operate in both depletion mode (negative VGS) and enhancement mode (positive VGS).
  • Enhancement-type MOSFET (E-MOSFET): No physical channel exists initially. Conduction requires a gate voltage greater than a threshold value (VGS > VT) to induce an inversion channel. This is the dominant type used in modern digital chips.
2. Construction of N-Channel Enhancement MOSFET
           Gate (Metal / Poly-Si)
                  | 
           +------+------+
           |  SiO2 Layer |  (Insulator)
  Drain    +-------------+                 Source
    |      |  n-Channel  |                   |
 +--+--+   +-------------+                +--+--+
 | n+  |==================================| n+  |
 +-----+                                  +-----+
 |                p-Substrate                   |
 +----------------------------------------------+
                         |
                     Substrate (Body)

(Schematic, not to scale)

3. Principle of Operation (N-Channel E-MOSFET)
  1. When VGS = 0: The two n+ regions (Drain and Source) are separated by the p-type substrate, forming two back-to-back PN junctions. No current flows (ID = 0).
  2. When VGS > 0 is applied: The positive gate potential repels holes downward from the substrate surface and attracts minority electrons toward the SiO2 interface.
  3. Inversion Layer Formation: When VGS exceeds the Threshold Voltage (VT), a continuous layer of electrons forms beneath the gate oxide, creating an induced n-type channel between Drain and Source.
  4. Drain Current Flow: With VDS > 0 applied, electrons flow freely from source to drain, resulting in drain current ID.
4. Characteristic Equations
  • Ohmic / Triode Region (VDS < VGS - VT):
    ID = mu_n Cox (W / L) [ (VGS - VT) VDS - 0.5 * VDS² ]
  • Saturation Region (VDS >= VGS - VT):
    ID = 0.5 mu_n Cox (W / L) (VGS - VT)²
5. Advantages
  • Exceptionally high input impedance (> 10^12 ohms).
  • Fast switching speeds with low static power consumption.
  • Primary building block of modern CMOS digital logic and computer processors.

Q.5 (a)

Question

Prepare the truth table for three basic logic gates.

Solution

Truth Tables for the Three Basic Logic Gates

The three fundamental logic gates are the AND, OR, and NOT gates.

1. AND Gate
  • Logic Expression: Y = A . B
  • Operation: Output is HIGH (1) only when all inputs are HIGH (1).

| Input A | Input B | Output Y (A . B) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |

2. OR Gate
  • Logic Expression: Y = A + B
  • Operation: Output is HIGH (1) if at least one input is HIGH (1).

| Input A | Input B | Output Y (A + B) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 1 |

3. NOT Gate (Inverter)
  • Logic Expression: Y = A' (or NOT A)
  • Operation: Output is the logical inverse of the single input.

| Input A | Output Y (A') | |:---:|:---:| | 0 | 1 | | 1 | 0 |

Q.5 (b)

Question

Explain the working principle of a field effect transistor (FET).

Solution

Working Principle of a Field Effect Transistor (FET)

A Junction Field Effect Transistor (JFET) is a three-terminal unipolar semiconductor device in which current through a conducting channel is modulated by an electric field established across reverse-biased junctions.

1. Basic Structure (N-Channel JFET)
                 Drain (D)
                     |
             +-------+-------+
             |  n-Channel    |
      Gate o-+ [p+]     [p+] +-o Gate
      (G)    |  |         |  |   (G)
             |  Depletion    |
             |    Region     |
             +-------+-------+
                     |
                 Source (S)

(Schematic, not to scale)

2. Working Principle
  • Zero Gate Bias (VGS = 0) with Small VDS:
    Applying a positive voltage VDS causes electrons to flow from source to drain. The channel acts as a linear resistor, and current ID increases proportionally with VDS.
  • Applying Reverse Gate Bias (VGS < 0):
    Connecting the p-type gate to a negative potential with respect to the source reverse-biases the two PN junctions. This expands the depletion regions inward into the n-channel, narrowing the effective cross-sectional area available for conduction.
  • Pinch-Off Phenomenon:
    As VDS increases, the reverse bias across the junction is highest near the drain end. When VDS reaches the Pinch-Off Voltage (Vp), the depletion layers approach each other, restricting the channel to a narrow path. Beyond pinch-off, ID saturates and remains constant at IDSS.
  • Shockley's Equation in the active saturation region:
    ID = IDSS * [ 1 - (VGS / Vp) ]²
    Thus, the output current ID is controlled by the input electric field set up by voltage VGS.

Q.5 (c)

Question

Discuss the resistor transistor logic (RTL)circuits for basic gates.

Solution

Resistor-Transistor Logic (RTL) Circuits for Basic Gates

Resistor-Transistor Logic (RTL) is an early family of digital logic circuits that implements Boolean operations using input resistors and bipolar junction transistors (BJTs).

1. RTL NOT Gate (Inverter)
  • Circuit Diagram:
                 +Vcc
                  |
                  / Rc
                  \ 
                  / 
                  +--------o Output Y = A'
                  | 
           RB     | C
  Input A o--/\/\-+---| BJT
                    | E
                   === GND

(Schematic, not to scale)

  • Operation:
  • When A = 0 (Low, 0 V): The base-emitter junction is unbiased. The transistor is in cut-off, no collector current flows, and Output Y ≈ +Vcc (Logic 1).
  • When A = 1 (High, +Vcc): Sufficient base current drives the transistor into saturation. Output Y = VCE(sat) ≈ 0.2 V (Logic 0).
  • Implements Y = A'.
2. RTL NOR Gate (Basic Gate in RTL)

In RTL, the basic multi-input building block is the NOR gate.

  • Circuit Diagram:
                      +Vcc
                       |
                       / Rc
                       \ 
                       / 
                       +-------------o Output Y = (A + B)'
                       |             |
             RB1       | C           | C
  Input A o--/\/\--+---| Q1   +------+---| Q2
                   |   | E    |      |   | E
                  === ===     |     === ===
                  GND GND     |     GND GND
             RB2              |
  Input B o--/\/\-------------+

(Schematic, not to scale)

  • Operation:
  • When A = 0 and B = 0: Both transistors Q1 and Q2 are in cut-off. Output is pulled HIGH to +Vcc (Logic 1).
  • When A = 1 OR B = 1 (or both): The respective transistor is driven into saturation, pulling the output down to VCE(sat) ≈ 0.2 V (Logic 0).
  • Truth table matches the NOR function: Y = (A + B)'.
3. RTL AND Gate

An RTL AND gate is constructed by feeding inputs through separate RTL inverters into an RTL NOR configuration, or by following a NOR gate with an inverter: Y = [ (A' + B')' ] = A . B (by De Morgan's Laws).

Q.5 (a) OR

Question

Draw the circuit diagram of OR gate with diodes.

Solution

Circuit Diagram of OR Gate Using Diodes

A two-input diode OR gate uses two diodes and a pull-down load resistor.

1. Circuit Schematic
              D1
  Input A o---|>|----+ 
                     |
              D2     +-----------o Output Y = A + B
  Input B o---|>|----+ 
                     | 
                     / 
                     \ R_L (Pull-down)
                     / 
                     | 
                    === GND

(Schematic, not to scale)

2. Working Principle
  • Let Logic 0 = 0 V (GND) and Logic 1 = +5 V.
  • A = 0 V, B = 0 V: Both diodes D1 and D2 are unbiased (OFF). No current flows through RL, so Output Y = 0 V (Logic 0).
  • A = 5 V, B = 0 V: Diode D1 is forward biased (conducting), while D2 is reverse biased. Output Y = 5 V - 0.7 V = 4.3 V (Logic 1).
  • A = 0 V, B = 5 V: Diode D2 is forward biased, D1 is reverse biased. Output Y = 4.3 V (Logic 1).
  • A = 5 V, B = 5 V: Both diodes conduct. Output Y = 4.3 V (Logic 1).

Q.5 (b) OR

Question

Show the implementation of OR gate logic with use of NAND gate.

Solution

Implementation of OR Gate Logic Using Only NAND Gates

The NAND gate is a universal gate, meaning any standard logic function can be synthesized using NAND gates alone.

1. Boolean Derivation (Using De Morgan's Theorem)

The Boolean expression for an OR gate is: Y = A + B

Taking double negation (involution law): Y = ((A + B)')'

Applying De Morgan's Second Theorem (A + B)' = A' . B': Y = (A' . B')'

This expression requires:

  1. Generating A' using a 2-input NAND gate with tied inputs.
  2. Generating B' using a second 2-input NAND gate with tied inputs.
  3. Feeding A' and B' into a third 2-input NAND gate.
2. Logic Circuit Diagram
  A o---+ 
        +---\ NAND 1
        |    )--------o A'
  A o---+---/          \
                        +---\ NAND 3
                             )--------o Y = (A'.B')' = A + B
  B o---+              /+---/
        +---\ NAND 2  / 
        |    )-------+ o B'
  B o---+---/

(Schematic, not to scale)

3. Verification Truth Table

| A | B | A' = (A.A)' | B' = (B.B)' | Y = (A' . B')' = A + B | |:---:|:---:|:---:|:---:|:---:| | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 |

The final output column matches the standard OR gate logic exactly.

Q.5 (c) OR

Question

Discuss the applications of EX-OR and EX-NOR gate with truth tables.

Solution

Applications and Truth Tables of EX-OR and EX-NOR Gates

Exclusive gates are specialized logic gates widely used in arithmetic, error detection, and digital communications.

1. Exclusive-OR (EX-OR / XOR) Gate
  • Boolean Expression: Y = A ⊕ B = A'B + AB'
  • Truth Table:

| Input A | Input B | Output Y (XOR) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

  • Primary Applications of EX-OR Gate:
  1. Binary Adders/Subtractors: Used to generate the Sum bit in Half Adders and Full Adders (Sum = A ⊕ B ⊕ Cin).
  2. Parity Generator and Checker: Computes odd or even parity bits for error detection during serial data transmission.
  3. Controlled Inverter: When one input is held at logic 1, the output is the complement of the other input (A ⊕ 1 = A'); when held at 0, it passes the input unchanged (A ⊕ 0 = A).
  4. Digital Comparator: Detects inequality between two binary bits (Output = 1 when inputs differ).

---

2. Exclusive-NOR (EX-NOR / XNOR) Gate
  • Boolean Expression: Y = (A ⊕ B)' = AB + A'B'
  • Truth Table:

| Input A | Input B | Output Y (XNOR) | |:---:|:---:|:---:| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |

  • Primary Applications of EX-NOR Gate:
  1. Equality Detector (Bit Comparator): The output is HIGH (1) only when both inputs are identical, making it the core component of multi-bit magnitude comparators.
  2. Even Parity Generation/Checking: Produces an active HIGH output when an even number of 1s are received.
  3. Phase Detectors in PLL: Used in Phase-Locked Loops to compare frequency and phase between two digital clock signals.

Frequently Asked Questions

What is the cut-in voltage for Silicon and Germanium PN junction diodes?

The typical cut-in (knee) voltage is approximately 0.7 V for a Silicon diode and approximately 0.3 V for a Germanium diode.

Why is voltage divider bias considered the best biasing circuit for a BJT?

Voltage divider bias provides excellent operating point stability because the collector current is independent of the transistor current gain (beta) and minimizes drift caused by temperature variations.

What makes the Schottky diode faster than a conventional PN junction diode?

A Schottky diode is a metal-semiconductor unipolar device that relies solely on majority carriers, eliminating minority carrier storage time and enabling picosecond reverse recovery speeds.

Why is the Common Collector configuration called an Emitter Follower?

The emitter terminal output voltage follows the base input voltage in phase and amplitude with a voltage gain close to unity (Av ≈ 1) and zero phase shift.

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