Basic Electronics (3110016) Semester 1 & 2 Winter 2025 GTU Solved Paper

Write key factors to achieve faithful amplifications.

Key Factors to Achieve Faithful Amplification

Faithful amplification means increasing the amplitude of an input AC signal without introducing any distortion or change in its waveform shape.

To ensure faithful amplification, three conditions must be strictly satisfied at all times during the signal cycle:

1. Proper Minimum Base-Emitter Voltage (Forward Bias of EBJ):
   The forward bias across the base-emitter junction must not fall below the cut-in voltage (0.7 V for Silicon, 0.3 V for Germanium) at any point during the negative peak of the AC input signal. Otherwise, the transistor enters the cut-off region, clipping the output waveform.

1. Adequate Minimum Collector-Emitter Voltage (VCE > VCE(sat)):
   The collector-to-emitter voltage must remain greater than the saturation voltage (typically 0.2 V for Silicon) at any point during the positive peak of the AC input signal. If VCE drops below VCE(sat), the transistor enters the saturation region, flattening the output waveform.

1. Proper Collector Current (IC > 0):
   A sufficient quiescent collector current ICQ must flow so that even during the most negative excursion of the input signal, the transistor remains completely within the active linear operating region.

Discuss the importances of operating points in transistor.

Importance of the Operating Point (Q-Point) in a Transistor

The operating point, commonly called the Quiescent point (Q-point), is the specific DC bias state of a transistor characterized by DC values (VCEQ, ICQ) in the absence of an applied AC input signal.

Importance and Significance

1. Ensures Operation in Active Linear Region:
   For faithful linear amplification, the transistor must remain in the active region at all times. Setting an accurate Q-point prevents the signal from crossing into saturation (where the output is clipped at the bottom) or cut-off (where the output is clipped at the top).

1. Maximizes Symmetrical Peak-to-Peak Output Swing:
   Positioning the Q-point precisely in the middle of the DC load line (VCEQ = VCC / 2) allows maximum unclipped signal voltage excursion in both positive and negative directions.

1. Thermal Stability and Prevention of Thermal Runaway:
   Transistor parameters (reverse leakage current ICBO, base-emitter voltage VBE, and current gain beta) are highly sensitive to temperature:

• ICBO doubles approximately every 10 °C rise.
• Increased ICBO causes an increase in total IC, raising internal junction temperature (P = VCE * IC).
• This cumulative heating can trigger thermal runaway, permanently destroying the transistor.
  A well-stabilized operating point prevents this destructive cycle and keeps the amplifier stable over varying ambient temperatures.

Discuss the load line analysis of transistor.

Load Line Analysis of a Transistor

Load line analysis is a graphical technique used to determine the exact DC operating point (Q-point) and analyze transistor operation under dynamic AC signal conditions on the output characteristic curves.

1. Derivation of DC Load Line Equation

Consider a Common Emitter circuit with collector resistor Rc connected to supply VCC. Applying Kirchhoff’s Voltage Law (KVL) around the collector-emitter output loop:

VCC - IC Rc - VCE = 0 Rearranging for collector current IC: IC = - (1 / Rc)

What is a stability factor?

Stability Factor in Transistors

The stability factor S measures how sensitive the collector current IC is to changes in internal, temperature-dependent transistor parameters.

1. Definition and Mathematical Expression

Primarily, the stability factor S is defined as the rate of change of collector current IC with respect to the reverse saturation current ICBO, keeping base-emitter voltage VBE and current gain beta constant:

S = (d IC) / (d ICBO) | (VBE, beta = constant)

General formula for stability factor in a biased BJT: S = (1 + beta) / [ 1 - beta * (d IB / d IC) ]

2. Significance

• An ideal circuit would have S = 1, meaning variations in leakage current do not get magnified.
• A smaller numerical value of S indicates superior bias stability against temperature fluctuations.

3. Other Stability Factors

Because temperature also affects VBE and beta, two additional stability factors are defined:

• S' = (d IC) / (d VBE) (sensitivity to base-emitter cut-in voltage)
• S'' = (d IC) / (d beta) (sensitivity to transistor current gain)

Explain the voltage divider biasing.

Voltage Divider Biasing

Voltage divider biasing (also called potential divider or universal bias) is the most widely adopted biasing technique because it makes the transistor operating point (Q-point) practically independent of transistor current gain (beta) and ambient temperature.

1. Circuit Diagram

                   +Vcc
                    |
             +------+------+
             |             |
             / R1          / Rc
             \             \
             /             /
             |       C     |
             +-----------|/ BJT
             |         B |\
             / R2          \ E
             \             |
             /             / RE
             |             \
             +------+------+
                    |
                   === GND

(Schematic, not to scale)

2. Circuit Analysis

Resistors R1 and R2 form a voltage divider across supply VCC.

• Base Voltage (VB):
  If the divider current through R1 and R2 is chosen much larger than the base current IB (I_divider >> IB):
  VB = VCC * [ R2 / (R1 + R2) ]

• Emitter Voltage (VE):
  VE = VB - VBE

• Emitter Current (IE):
  IE = VE / RE = (VB - VBE) / RE

• Collector Current (IC):
  Since IC ≈ IE:
  IC ≈ (VB - VBE) / RE

• Collector-to-Emitter Voltage (VCE):
  Applying KVL around the output loop:
  VCE = VCC - IC Rc - IE RE ≈ VCC - IC * (Rc + RE)

3. Why It Provides Excellent Stability

Notice that the expression for IC does not contain the parameter beta. Since VB is determined strictly by stable external resistors R1 and R2, and VBE (0.7 V) is negligible compared to VB, the collector current IC remains rock solid against temperature changes and unit-to-unit transistor variations.

Discuss the construction and operation of Schottky diode.

Schottky Diode: Construction and Operation

A Schottky diode (named after Walter H. Schottky) is a unipolar, majority-carrier semiconductor diode characterized by an ultra-fast switching speed and a low forward voltage drop.

1. Construction

Unlike standard PN junction diodes that interface two semiconductors, a Schottky diode is fabricated by forming a direct contact between a metal (such as platinum, tungsten, gold, or molybdenum) and an n-type semiconductor (typically silicon).

                  Metal-Semiconductor Junction
            Anode             |
           (Metal)            |       n-type Silicon (Cathode)
       +---------------+      |      +------------------------+
  o----| Platinum / Al |=============|   n-type Epitaxial     |----o
       +---------------+      |      +------------------------+
                              |      (Heavily doped n+ Substrate)

(Schematic, not to scale)

• Metal Layer: Acts as the Anode.
• N-type Silicon: Acts as the Cathode.
• This metal-semiconductor boundary creates a rectifying contact called a Schottky Barrier.

2. Working Principle and Operation

• Unbiased Condition:
  The conduction band electrons in the n-type semiconductor have higher average thermal energy than the electrons in the metal. When joined, electrons from the n-side flow into the metal until electrostatic equilibrium is achieved, leaving behind positive uncompensated donor ions in the n-region and building a depletion barrier across the interface.

• Forward Biasing:
  Applying a positive voltage to the metal relative to the n-type semiconductor lowers the built-in barrier. Electrons in the n-region easily cross into the metal, giving rise to forward current.
• Key Feature: The forward knee voltage is very low—typically 0.2 V to 0.3 V (compared to 0.7 V for a conventional silicon PN junction).

• Reverse Biasing:
  Applying a negative voltage to the metal raises the barrier height. Free electrons cannot cross the barrier, resulting in a small reverse leakage current.

3. Major Advantages

1. Zero Minority-Carrier Storage Time: Because conduction is entirely due to majority carriers (electrons), there are no minority carriers to recombine when switching off. The reverse recovery time trr is negligible (in picoseconds).
2. Low Forward Conduction Loss: Due to the smaller cut-in voltage (0.2–0.3 V).

4. Applications

• High-frequency RF mixers and detectors.
• High-efficiency Switched-Mode Power Supplies (SMPS).
• Clamping diodes in high-speed digital logic (Schottky TTL).

What are the roles of coupling capacitor and bypass capacitor in amplifier circuits?

Roles of Coupling Capacitor and Bypass Capacitor in Amplifier Circuits

Capacitors present frequency-dependent impedance given by Xc = 1 / (2 pi f * C). For DC (f = 0 Hz), impedance is infinite (open circuit); for AC signals, impedance is small.

1. Role of Coupling Capacitor (Cin and Cout)

• DC Isolation: Blocks DC voltages from passing between adjacent stages or from the input source / output load into the transistor base and collector.
• Preserves Bias Points: Prevents external source resistance or load resistance from altering the transistor's DC operating point (Q-point).
• AC Signal Transmission: Provides a low-impedance path to couple the alternating input signal into the base and the amplified AC output signal to the load.

2. Role of Emitter Bypass Capacitor (C_E)

• AC Grounding: Placed in parallel with the emitter resistor RE. For AC signal frequencies, its capacitive reactance is negligible (Xc << RE), effectively shorting AC signals straight to ground.
• Prevents AC Negative Feedback: Without CE, the AC current flowing through RE develops an opposing AC voltage (ic * RE), which reduces the effective base-emitter signal drive (negative feedback).
• Maximizes AC Voltage Gain: By bypassing RE for AC signals, the full signal drop appears across the base-emitter junction, maintaining maximum voltage gain.

Discuss the operation of common collector circuits analysis.

Operation and Analysis of Common Collector (CC) Circuit

The Common Collector circuit, universally known as the Emitter Follower, has its collector terminal connected to AC ground, using the base as input and taking output from the emitter.

1. Circuit Schematic

                  +Vcc
                   |
                   +---------------+ (Collector at AC ground)
                   |               |
                  / R1             |
                  \                |
                  /            C |/ 
      Vin o--||---+------------|    BJT
                  |            B |\ 
                  / R2             \ E
                  \                |
                  /                +---||----> Vo (Output)
                  |                |
                 ===              / RE
                 GND              \ 
                                  / 
                                   |
                                  === GND

(Schematic, not to scale)

2. Circuit Analysis

• Voltage Gain (Av):
  Applying KVL around the input-output loop:
  vin = ib hie + ie RE
vo = ie RE = (1 + beta) ib * RE
  Therefore:
  Av = vo / vin = [ (1 + beta) RE ] / [ hie + (1 + beta) RE ]
  Since (1 + beta) * RE >> hie, the voltage gain is:
  Av ≈ 1 (typically between 0.95 and 0.99, slightly less than unity).

• Phase Relationship:
  The output voltage at the emitter follows the input signal in both amplitude and phase (0° phase shift, hence called the Emitter Follower).

• Input Impedance (Zin):
  Zin = R1 || R2 || [ hie + (1 + beta) * RE ]
  The input impedance is very high (hundreds of kilo-ohms).

• Output Impedance (Zout):
  Zout = RE || [ (Rs + hie) / (1 + beta) ]
  The output impedance is very low (tens of ohms).

3. Primary Application

Due to high input impedance and low output impedance, it is extensively used as a buffer amplifier for impedance matching between a high-impedance source and a low-impedance load.

Shows parametric comparisons between of CE, CB and CC.

Parametric Comparison Between CE, CB, and CC Configurations

The table below summarizes the key operational characteristics and AC parameters of BJT amplifier configurations:

| Parameter / Feature | Common Base (CB) | Common Emitter (CE) | Common Collector (CC) | |---|---|---|---| | Common Terminal | Base | Emitter | Collector | | Input Terminal | Emitter | Base | Base | | Output Terminal | Collector | Collector | Emitter | | Input Impedance (Zin) | Very Low (~ 20 to 50 ohms) | Medium (~ 1 to 2 k-ohms) | Very High (~ 100 to 500 k-ohms) | | Output Impedance (Zout) | Very High (~ 1 M-ohm) | Moderate (~ 50 k-ohms) | Very Low (~ 20 to 100 ohms) | | Current Gain | Less than unity (alpha < 1) | High (beta ≈ 50 to 300) | High (gamma = 1 + beta) | | Voltage Gain | High | High | Approximately unity (< 1) | | Power Gain | Moderate | Highest | Low to Moderate | | Phase Shift (Input to Output) | 0° (In-phase) | 180° (Out-of-phase) | 0° (In-phase) | | Primary Application | High-frequency RF circuits | General audio/voltage amplifiers | Buffer and impedance matching |

Draw the circuits of seven segment LED display.

Seven Segment LED Display Circuit

A seven-segment display consists of seven individual light-emitting diodes arranged in a figure-8 pattern (labeled a through g), plus an optional decimal point (dp).

1. Segment Arrangement

       -- a --
     |         |
     f         b
     |         |
       -- g --
     |         |
     e         c
     |         |
       -- d --    * dp

2. Circuit Configurations (Common Anode and Common Cathode)

Common Cathode (CC) Configuration:        Common Anode (CA) Configuration:

        a  b  c  d  e  f  g                     +Vcc (Common)
        |  |  |  |  |  |  |                           |
        v  v  v  v  v  v  v                           +-------+
       --- --- --- --- --- ---                        |       |
        |  |  |  |  |  |  |                          ---     ---
        +--+--+--+--+--+--+                          / \     / \
                 |                                  --+--   --+--
                === GND                               |       |
     (Active HIGH inputs:                           R /     R /
      Logic 1 turns segment ON)                     \       \ 
                                                      |       |
                                                      a       b  ... (inputs)
                                            (Active LOW inputs:
                                             Logic 0 turns segment ON)

(Schematic, not to scale)

What are the differences between FET and BJT?

Differences Between FET and BJT

| Parameter / Feature | Bipolar Junction Transistor (BJT) | Field Effect Transistor (FET) | |---|---|---| | Full Form | Bipolar Junction Transistor | Field Effect Transistor | | Carrier Action | Bipolar: Conduction involves both electrons and holes. | Unipolar: Conduction involves only majority carriers (electrons or holes). | | Control Type | Current-controlled device (output IC depends on input IB). | Voltage-controlled device (output ID depends on input VGS). | | Input Impedance | Low to moderate (~ a few kilo-ohms). | Extremely high (~ 10^8 to 10^14 ohms) due to reverse-biased gate or insulating oxide. | | Terminals | Base (B), Emitter (E), Collector (C). | Gate (G), Source (S), Drain (D). | | Noise Performance | Higher noise level. | Much lower electrical noise (ideal for input stages). | | Thermal Stability | Negative temperature coefficient (prone to thermal runaway). | Positive temperature coefficient (immune to thermal runaway). | | Fabrication Size | Relatively large silicon area. | Extremely small and compact; highly suitable for VLSI / IC design. | | Offset Voltage | Has small collector-emitter offset voltage in saturation. | No offset voltage across drain and source. |

Write short note on MOSFET.

Short Note on MOSFET

A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a unipolar, voltage-controlled four-terminal device (Drain, Source, Gate, and Body/Substrate) where the gate is electrically insulated from the conducting channel by a thin layer of silicon dioxide (SiO2).

1. Classification of MOSFETs

• Depletion-type MOSFET (D-MOSFET): A physical channel exists at zero gate bias (VGS = 0). It can operate in both depletion mode (negative VGS) and enhancement mode (positive VGS).
• Enhancement-type MOSFET (E-MOSFET): No physical channel exists initially. Conduction requires a gate voltage greater than a threshold value (VGS > VT) to induce an inversion channel. This is the dominant type used in modern digital chips.

2. Construction of N-Channel Enhancement MOSFET

           Gate (Metal / Poly-Si)
                  | 
           +------+------+
           |  SiO2 Layer |  (Insulator)
  Drain    +-------------+                 Source
    |      |  n-Channel  |                   |
 +--+--+   +-------------+                +--+--+
 | n+  |==================================| n+  |
 +-----+                                  +-----+
 |                p-Substrate                   |
 +----------------------------------------------+
                         |
                     Substrate (Body)

(Schematic, not to scale)

3. Principle of Operation (N-Channel E-MOSFET)

1. When VGS = 0: The two n+ regions (Drain and Source) are separated by the p-type substrate, forming two back-to-back PN junctions. No current flows (ID = 0).
2. When VGS > 0 is applied: The positive gate potential repels holes downward from the substrate surface and attracts minority electrons toward the SiO2 interface.
3. Inversion Layer Formation: When VGS exceeds the Threshold Voltage (VT), a continuous layer of electrons forms beneath the gate oxide, creating an induced n-type channel between Drain and Source.
4. Drain Current Flow: With VDS > 0 applied, electrons flow freely from source to drain, resulting in drain current ID.

4. Characteristic Equations

• Ohmic / Triode Region (VDS < VGS - VT):
  ID = mu_n Cox (W / L) [ (VGS - VT) VDS - 0.5 * VDS² ]
• Saturation Region (VDS >= VGS - VT):
  ID = 0.5 mu_n Cox (W / L) (VGS - VT)²

5. Advantages

• Exceptionally high input impedance (> 10^12 ohms).
• Fast switching speeds with low static power consumption.
• Primary building block of modern CMOS digital logic and computer processors.

Prepare the truth table for three basic logic gates.

Truth Tables for the Three Basic Logic Gates

The three fundamental logic gates are the AND, OR, and NOT gates.

1. AND Gate

• Logic Expression: Y = A . B
• Operation: Output is HIGH (1) only when all inputs are HIGH (1).

| Input A | Input B | Output Y (A . B) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |

2. OR Gate

• Logic Expression: Y = A + B
• Operation: Output is HIGH (1) if at least one input is HIGH (1).

| Input A | Input B | Output Y (A + B) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 1 |

3. NOT Gate (Inverter)

• Logic Expression: Y = A' (or NOT A)
• Operation: Output is the logical inverse of the single input.

| Input A | Output Y (A') | |:---:|:---:| | 0 | 1 | | 1 | 0 |

Explain the working principle of a field effect transistor (FET).

Working Principle of a Field Effect Transistor (FET)

A Junction Field Effect Transistor (JFET) is a three-terminal unipolar semiconductor device in which current through a conducting channel is modulated by an electric field established across reverse-biased junctions.

1. Basic Structure (N-Channel JFET)

                 Drain (D)
                     |
             +-------+-------+
             |  n-Channel    |
      Gate o-+ [p+]     [p+] +-o Gate
      (G)    |  |         |  |   (G)
             |  Depletion    |
             |    Region     |
             +-------+-------+
                     |
                 Source (S)

(Schematic, not to scale)

2. Working Principle

• Zero Gate Bias (VGS = 0) with Small VDS:
  Applying a positive voltage VDS causes electrons to flow from source to drain. The channel acts as a linear resistor, and current ID increases proportionally with VDS.

• Applying Reverse Gate Bias (VGS < 0):
  Connecting the p-type gate to a negative potential with respect to the source reverse-biases the two PN junctions. This expands the depletion regions inward into the n-channel, narrowing the effective cross-sectional area available for conduction.

• Pinch-Off Phenomenon:
  As VDS increases, the reverse bias across the junction is highest near the drain end. When VDS reaches the Pinch-Off Voltage (Vp), the depletion layers approach each other, restricting the channel to a narrow path. Beyond pinch-off, ID saturates and remains constant at IDSS.

• Shockley's Equation in the active saturation region:
  ID = IDSS * [ 1 - (VGS / Vp) ]²
  Thus, the output current ID is controlled by the input electric field set up by voltage VGS.

Discuss the resistor transistor logic (RTL)circuits for basic gates.

Resistor-Transistor Logic (RTL) Circuits for Basic Gates

Resistor-Transistor Logic (RTL) is an early family of digital logic circuits that implements Boolean operations using input resistors and bipolar junction transistors (BJTs).

1. RTL NOT Gate (Inverter)

• Circuit Diagram:

                 +Vcc
                  |
                  / Rc
                  \ 
                  / 
                  +--------o Output Y = A'
                  | 
           RB     | C
  Input A o--/\/\-+---| BJT
                    | E
                   === GND

(Schematic, not to scale)

• Operation:
• When A = 0 (Low, 0 V): The base-emitter junction is unbiased. The transistor is in cut-off, no collector current flows, and Output Y ≈ +Vcc (Logic 1).
• When A = 1 (High, +Vcc): Sufficient base current drives the transistor into saturation. Output Y = VCE(sat) ≈ 0.2 V (Logic 0).
• Implements Y = A'.

2. RTL NOR Gate (Basic Gate in RTL)

In RTL, the basic multi-input building block is the NOR gate.

• Circuit Diagram:

                      +Vcc
                       |
                       / Rc
                       \ 
                       / 
                       +-------------o Output Y = (A + B)'
                       |             |
             RB1       | C           | C
  Input A o--/\/\--+---| Q1   +------+---| Q2
                   |   | E    |      |   | E
                  === ===     |     === ===
                  GND GND     |     GND GND
             RB2              |
  Input B o--/\/\-------------+

(Schematic, not to scale)

• Operation:
• When A = 0 and B = 0: Both transistors Q1 and Q2 are in cut-off. Output is pulled HIGH to +Vcc (Logic 1).
• When A = 1 OR B = 1 (or both): The respective transistor is driven into saturation, pulling the output down to VCE(sat) ≈ 0.2 V (Logic 0).
• Truth table matches the NOR function: Y = (A + B)'.

3. RTL AND Gate

An RTL AND gate is constructed by feeding inputs through separate RTL inverters into an RTL NOR configuration, or by following a NOR gate with an inverter: Y = [ (A' + B')' ] = A . B (by De Morgan's Laws).

Draw the circuit diagram of OR gate with diodes.

Circuit Diagram of OR Gate Using Diodes

A two-input diode OR gate uses two diodes and a pull-down load resistor.

1. Circuit Schematic

              D1
  Input A o---|>|----+ 
                     |
              D2     +-----------o Output Y = A + B
  Input B o---|>|----+ 
                     | 
                     / 
                     \ R_L (Pull-down)
                     / 
                     | 
                    === GND

(Schematic, not to scale)

2. Working Principle

• Let Logic 0 = 0 V (GND) and Logic 1 = +5 V.
• A = 0 V, B = 0 V: Both diodes D1 and D2 are unbiased (OFF). No current flows through RL, so Output Y = 0 V (Logic 0).
• A = 5 V, B = 0 V: Diode D1 is forward biased (conducting), while D2 is reverse biased. Output Y = 5 V - 0.7 V = 4.3 V (Logic 1).
• A = 0 V, B = 5 V: Diode D2 is forward biased, D1 is reverse biased. Output Y = 4.3 V (Logic 1).
• A = 5 V, B = 5 V: Both diodes conduct. Output Y = 4.3 V (Logic 1).

Show the implementation of OR gate logic with use of NAND gate.

Implementation of OR Gate Logic Using Only NAND Gates

The NAND gate is a universal gate, meaning any standard logic function can be synthesized using NAND gates alone.

1. Boolean Derivation (Using De Morgan's Theorem)

The Boolean expression for an OR gate is: Y = A + B

Taking double negation (involution law): Y = ((A + B)')'

Applying De Morgan's Second Theorem (A + B)' = A' . B': Y = (A' . B')'

This expression requires:

1. Generating A' using a 2-input NAND gate with tied inputs.
2. Generating B' using a second 2-input NAND gate with tied inputs.
3. Feeding A' and B' into a third 2-input NAND gate.

2. Logic Circuit Diagram

  A o---+ 
        +---\ NAND 1
        |    )--------o A'
  A o---+---/          \
                        +---\ NAND 3
                             )--------o Y = (A'.B')' = A + B
  B o---+              /+---/
        +---\ NAND 2  / 
        |    )-------+ o B'
  B o---+---/

(Schematic, not to scale)

3. Verification Truth Table

| A | B | A' = (A.A)' | B' = (B.B)' | Y = (A' . B')' = A + B | |:---:|:---:|:---:|:---:|:---:| | 0 | 0 | 1 | 1 | 0 | | 0 | 1 | 1 | 0 | 1 | | 1 | 0 | 0 | 1 | 1 | | 1 | 1 | 0 | 0 | 1 |

The final output column matches the standard OR gate logic exactly.

Discuss the applications of EX-OR and EX-NOR gate with truth tables.

Applications and Truth Tables of EX-OR and EX-NOR Gates

Exclusive gates are specialized logic gates widely used in arithmetic, error detection, and digital communications.

1. Exclusive-OR (EX-OR / XOR) Gate

• Boolean Expression: Y = A ⊕ B = A'B + AB'
• Truth Table:

| Input A | Input B | Output Y (XOR) | |:---:|:---:|:---:| | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

• Primary Applications of EX-OR Gate:

1. Binary Adders/Subtractors: Used to generate the Sum bit in Half Adders and Full Adders (Sum = A ⊕ B ⊕ Cin).
2. Parity Generator and Checker: Computes odd or even parity bits for error detection during serial data transmission.
3. Controlled Inverter: When one input is held at logic 1, the output is the complement of the other input (A ⊕ 1 = A'); when held at 0, it passes the input unchanged (A ⊕ 0 = A).
4. Digital Comparator: Detects inequality between two binary bits (Output = 1 when inputs differ).

---

2. Exclusive-NOR (EX-NOR / XNOR) Gate

• Boolean Expression: Y = (A ⊕ B)' = AB + A'B'
• Truth Table:

| Input A | Input B | Output Y (XNOR) | |:---:|:---:|:---:| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 1 |

• Primary Applications of EX-NOR Gate:

1. Equality Detector (Bit Comparator): The output is HIGH (1) only when both inputs are identical, making it the core component of multi-bit magnitude comparators.
2. Even Parity Generation/Checking: Produces an active HIGH output when an even number of 1s are received.
3. Phase Detectors in PLL: Used in Phase-Locked Loops to compare frequency and phase between two digital clock signals.